The Community for Technology Leaders
2013 18th IEEE European Test Symposium (ETS) (2004)
Corsica, France
May 23, 2004 to May 26, 2004
ISBN: 0-7695-2119-3
TABLE OF CONTENTS

Foreword (PDF)

pp. viii
Debug and Diagnosis

At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults (Abstract)

Artur Jutman , Tallinn University of Technology
pp. 2-7
Analog Measurement Techniques

Accurate Tap-Delay Measurements Using a Differential Oscillation Technique (Abstract)

O. Petre , MESA+ Research Institute, The Netherlands
H. G. Kerkhoff , MESA+ Research Institute, The Netherlands
pp. 10-15

Delay Chain Based Programmable Jitter Generator (Abstract)

Jien-Chung Lo , Univ. of Rhode Island, Kingston
Peilin Song , IBM T.J. Watson Research Center, Yorktown Heights, NY
Tian Xia , Univ. of Vermont, Burlington, VT
Keith A. Jenkins , IBM T.J. Watson Research Center, Yorktown Heights, NY
pp. 16-21
Design for Dependability

Application of Local Design-for-Reliability Techniques for Reducing Wear-out Degradation of CMOS Combinational Logic Circuits (Abstract)

Adit D. Singh , Auburn University, AL
Xiangdong Xuan , Georgia Institute of Technology, Atlanta
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta
pp. 24-29

A New Self-Checking Multiplier by Use of a Code-Disjoint Sum-Bit Duplicated Adder (Abstract)

D. Marienfeld , University of Potsdam, Germany
M. G?ssel , University of Potsdam, Germany
V. Ocheretnij , University of Potsdam, Germany
E. S. Sogomonyan , University of Potsdam, Germany
pp. 30-35
ATE Hardware and Software

Software Development for an Open Architecture Test System (Abstract)

Ankan Pramanick , Advantest R&D Center Inc.
Bruce R. Parnas , Advantest R&D Center Inc.
Toshiaki Adachi , Advantest R&D Center Inc.
Mark Elston , Advantest R&D Center Inc.
pp. 38-43
Timing and Delay Testing

Delay Fault Testing and Silicon Debug Using Scan Chains (Abstract)

Antony Sebastine , The University of Texas at Austin
Ramyanshu Datta , The University of Texas at Austin
Jacob A. Abraham , The University of Texas at Austin
pp. 46-51

Manufacturing-Oriented Testing of Delay Faults in the Logic Architecture of Symmetrical FPGAs (Abstract)

Olivier H?ron , Universit? Montpellier II / CNRS, France
Serge Pravossoudovitch , Universit? Montpellier II / CNRS, France
Patrick Girard , Universit? Montpellier II / CNRS, France
Michel Renovell , Universit? Montpellier II / CNRS, France
pp. 52-57
MEMS Testing

Electrically-Induced Thermal Stimuli for MEMS Testing (Abstract)

N. Dumas , Universit? de Montpellier II / CNRS, France
P. Nouet , Universit? de Montpellier II / CNRS, France
F. Aza? , Universit? de Montpellier II / CNRS, France
L. Latorre , Universit? de Montpellier II / CNRS, France
pp. 60-65

MEMS Built-In-Self-Test Using MLS (Abstract)

S. Mir , TIMA Laboratory, France
A. Dhayni , TIMA Laboratory, France
L. Rufer , TIMA Laboratory, France
pp. 66-71

Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems (Abstract)

Sule Ozev , Duke University, Durham, NC
Fei Su , Duke University, Durham, NC
Krishnendu Chakrabarty , Duke University, Durham, NC
pp. 72-77
Embedded Core Testing

User-Constrained Test Architecture Design for Modular SOC Testing (Abstract)

Bruno Rouzeyre , LIRMM, France
Ludovic Krundel , Universit? Montpellier II, France
Erik Jan Marinissen , Philips Research Laboratories, The Netherlands
Sandeep Kumar Goel , Philips Research Laboratories, The Netherlands
Marie-Lise Flottes , LIRMM, France
pp. 80-85

Pipelined Test of SOC Cores Through Test Data Transformations (Abstract)

Ozgur Sinanoglu , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 86-91
Test Resource Partitioning

Relating Entropy Theory to Test Data Compression (Abstract)

Kedarnath J. Balakrishnan , University of Texas, Austin
Nur A. Touba , University of Texas, Austin
pp. 94-99

A Compression-Driven Test Access Mechanism Design Approach (Abstract)

Bashir M. Al-Hashimi , University of Southampton, UK
Paul Theo Gonciari , University of Southampton, UK
pp. 100-105
Fault Simulation and Verification

Enhanced 3-Valued Logic/Fault Simulation for Full Scan Circuits using Implicit Logic Values (Abstract)

Kewal K. Saluja , University of Wisconsin-Madison
Seiji Kajihara , Kyushu Institute of Technology, Japan
Sudhakar M. Reddy , University of Iowa, Iowa City
pp. 108-113

Signal Integrity Verification using High Speed Monitors (Abstract)

Joan Figueras , Universitat Politecnica de Catalunya-UPC, Barcelona, Spain
Victor Avenda? , Optics and Electronics-INAOE, Puebla, Mexico
Victor Champac , Optics and Electronics-INAOE, Puebla, Mexico
pp. 114-119
Analog BIST

Towards a BIST Technique for Noise Figure Evaluation (Abstract)

Luigi Carro , Universidade Federal do Rio Grande do Sul, Brazil
Marcelo Negreiros , Universidade Federal do Rio Grande do Sul, Brazil
Altamiro A. Susin , Universidade Federal do Rio Grande do Sul, Brazil
pp. 122-126

A New BIST Scheme for 5GHz Low Noise Amplifiers (Abstract)

Bruce C. Kim , Arizona State University, Tempe, AZ
Jee-Youl Ryu , Arizona State University, Tempe, AZ
Iboun Sylla , Texas Instruments, Inc., Dallas, Texas
pp. 127-132

All-Pass SC Biquad Reconfiguration Scheme for Oscillation Based Analog BIST (Abstract)

Franc Novak , Jozef Stefan Institute
Uros Kac , Jozef Stefan Institute
pp. 133-138
Memory Testing

Dynamic Read Destructive Fault in Embedded-SRAMs: Analysis and March Test Solution (Abstract)

Patrick Girard , Universit? de Montpellier II / CNRS, France
Serge Pravossoudovitch , Universit? de Montpellier II / CNRS, France
Luigi Dilillo , Universit? de Montpellier II / CNRS, France
Arnaud Virazel , Universit? de Montpellier II / CNRS, France
Simone Borri , Infineon Technologies France
Magali Hage-Hassan , Infineon Technologies France
pp. 140-145

Tests for Address Decoder Delay Faults in RAMs due to Inter-Gate Opens (Abstract)

Ad J. van de Goor , Delft University of Technology, The Netherlands
Said Hamdioui , Philips Semiconductor Crolles R&D, France; Delft University of Technology, The Netherlands
Zaid Al-Ars , CatRam Solutions, The Netherlands; Delft University of Technology, The Netherlands
pp. 146-151
ATPG and High-Level Test

Automatic Test Pattern Generation for Resistive Bridging Faults (Abstract)

Piet Engelke , Albert-Ludwigs-University, Germany
Bernd Becker , Albert-Ludwigs-University, Germany
Michel Renovell , LIRMM - UMII, France
Ilia Polian , Albert-Ludwigs-University, Germany
pp. 160-165
Advances in DfT

A Design Methodology to Realize Delay Testable Controllers Using State Transition Information (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology, Japan
Tsuyoshi Iwagaki , Nara Institute of Science and Technology, Japan
Satoshi Ohtake , Nara Institute of Science and Technology, Japan
pp. 168-173

An Efficient Scan Tree Design for Test Time Reduction (Abstract)

Y. Bonhomme , Nara Institute of Science and Technology
P. Girard , Universit? Montpellier II/CNRS, France
T. Yoneda , Nara Institute of Science and Technology
H. Fujiwara , Nara Institute of Science and Technology
pp. 174-179

Author Index (PDF)

pp. 180-181
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