2008 IEEE Fourth International Conference on eScience (2008)
Dec. 7, 2008 to Dec. 12, 2008
The EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is focused upon delivering a production level e-Infrastructure to meet the challenges facing the semiconductor industry in dealing with the next generation of 'atomic-scale' transistor devices. This scale means that previous assumptions on the uniformity of transistor devices in electronics circuit and systems design are no longer valid, and the industry as a whole must deal with variability throughout the design process. Infrastructures to tackle this problem must provide seamless access to very large HPC resources for computationally expensive simulation of statistic ensembles of microscopically varying physical devices, and manage the many hundreds of thousands of files and meta-data associated with these simulations. A key challenge in undertaking this is in protecting the intellectual property associated with the data, simulations and design process as a whole. In this paper we present the nanoCMOS infrastructure and outline an evaluation undertaken on the Storage Resource Broker (SRB) and the Andrew File System (AFS) considering in particular the extent that they meet the performance and security requirements of the nanoCMOS domain. We also describe how metadata management is supported and linked to simulations and results in a scalable and secure manner.
Andrew File System, Storage Resource Broker, nanoCMOS electronics, security, performance
G. Stewart, C. Davenhall, S. Roy, M. Jones, J. Watt, G. Roy, C. Bayliss, B. Harbulot, C. Millar, R. O. Sinnott, A. Asenov, "Secure, Performance-Oriented Data Management for nanoCMOS Electronics", 2008 IEEE Fourth International Conference on eScience, vol. 00, no. , pp. 87-94, 2008, doi:10.1109/eScience.2008.21