The Community for Technology Leaders
European Design and Test Conference (1997)
Mar. 17, 1997 to Mar. 20, 1997
ISSN: 1066-1409
ISBN: 0-8186-7786-4
TABLE OF CONTENTS

Keynote Speakers (PDF)

pp. xxii

Welcome Message (PDF)

pp. xxix

Tutorials (PDF)

pp. xxxi

Best Paper Award (PDF)

pp. xxxv

List of Reviewers (PDF)

pp. xxxvi
Session 1A: System Analysis Techniques and Applications

RATAN: A Tool for Rate Analysis and Rate Constraint Debugging for Embedded Systems (Abstract)

Ali Dasdan , Dept. of Comp. Sci., Univ. of Illinois, IL, USA
Rajesh K. Gupta , Dept. of Info. & Comp. Sci., Univ. of California, Irvine, CA, USA
Anmol Mathur , Silicon Graphics Inc., Mountain View, CA, USA
pp. 2

Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications (Abstract)

Alexandru Nicolau , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Preeti Ranjan Panda , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Nikil D. Dutt , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 7
Session 1B: Sequential ATPG

Sequential ATPG (PDF)

pp. null

Sequential Circuit Test Generation Using Dynamic State Traversal (Abstract)

Michael S. Hsiao , University of Illinois, Illinois, USA
Janak H. Patel , University of Illinois, Illinois, USA
Elizabeth M. Rudnick , University of Illinois, Illinois, USA
pp. 22

MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits (Abstract)

Y. Bertrand , Univ. Montpellier II / CNRS, Montpellier, FRANCE
A. Dargelas , Univ. Montpellier II / CNRS, Montpellier, FRANCE
C. Gauthron , COMPASS Design Automation, Sophia-Antipolis, FRANCE
pp. 29

New Static Compaction Techniques of Test Sequences for Sequential Circuits (Abstract)

M. Rebaudengo , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
F. Corno , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 37
Session 1C: Design and Design Methodology for Analog Circuits

A Methodology for Designing Continuous-Time Sigma-Delta Modulators (Abstract)

Philippe Benabes , Ecole Superieure d'Electr., Gif-sur-Yvette, France
Richard Kielbasa , Ecole Superieure d'Electr., Gif-sur-Yvette, France
Mansour Keramat , Ecole Superieure d'Electr., Gif-sur-Yvette, France
pp. 46

A CMOS Low Voltage, High Gain Op-Amp (Abstract)

Guo-Neng Lu , Universit? Pierre et Marie Curie ( PARIS VI )
Gerard Sou , Universit? Pierre et Marie Curie ( PARIS VI )
pp. 51

High-Level Synthesis of Analog Sensor Interface Front-Ends (Abstract)

W. Van Bokhoven , Eindhoven University of Technology, Eindhoven, The Netherlands
S. Donnay , Katholieke Universiteit Leuven, Heverlee, Belgium
D. Leenaerts , Eindhoven University of Technology, Eindhoven, The Netherlands
G. Gielen , Katholieke Universiteit Leuven, Heverlee, Belgium
W. Kruiskamp , Eindhoven University of Technology, Eindhoven, The Netherlands
W. Sansen , Katholieke Universiteit Leuven, Heverlee, Belgium
pp. 56
Session 2A: Panel P1
Session 2B: Advances in Built-In Self-Test

Structural BIST Insertion Using Behavioral Test Analysis (Abstract)

M. Nourani , Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
C. Papachristou , Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
pp. 64

On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs (Abstract)

Christian Dufaza , LIRMM, Montpellier, FRANCE
Yervant Zorian , Logic Vision, Inc., CA, USA
pp. 69

Cellular Automata for Generating Deterministic Test Sequences (Abstract)

Spyros Tragoudas , Computer Science Dept., Southern Illinois University, IL, USA
Dimitrios Kagaris , Electrical Engineering Dept., Southern Illinois University, IL, USA
pp. 77
Session 2C: Synthesis of Controllers

Fast Controllers for Data Dominated Applications (Abstract)

Andre Hertwig , University of Stuttgart, Germany
Hans-Joachim Wunderlich , University of Stuttgart, Germany
pp. 84

Random Benchmark Circuits with Controlled Attributes (Abstract)

Hiroyuki Kurokawa , Research & Development, JUSTSYSTEM Corporation, Japan
Kensuke Hino , Industria1 Instrumentation & Control Systems Department, TOSHIBA Corporation, Japan
Sunao Sawada , Dept of Computer Science & Communication Engineering, Kyushu University, Japan
Kazuo Iwama , Dept of Computer Science & Communication Engineering, Kyushu University, Japan
pp. 90

Technology Mapping of Speed-Independent Circuits Based on Combinational Decomposition and Resynthesis (Abstract)

Luciano Lavagno , Politecnico di Torino, Torino, Italy
Jordi Cortadella , Universit Politecnica de Catalunya, Barcelona, Spain
Alex Kondratyev , The University of Aizu, Aizu- Wakamatsu, Japan
Michael Kishinevsky , The University of Aizu, Aizu- Wakamatsu, Japan
Alex Yakovlev , University of Newcastle upon Tyne, England
pp. 98
Session 2D: Microsystems Design I

Generation of the HDL-A-Model of a Micromembrane from Its Finite-Element-Description (Abstract)

Manfred Glesner , Darmstadt University of Technology, Institute of Microelectronic Systems, Darmstadt, Germany
Nicu Sebe , University Bucharest, Romania
A. Manolescu , University Bucharest, Romania
Bernard Courtois , INPG / TIMA, Grenoble, France
Santiago Marco , University of Barcelona, Spain
Josep Samitier , University of Barcelona, Spain
Klaus Hofmann , Darmstadt University of Technology, Institute of Microelectronic Systems, Darmstadt, Germany
Jean-Michel Karam , INPG / TIMA, Grenoble, France
pp. 108

Microsystem Design Using Simulator Coupling (Abstract)

P. Schwarz , Fraunhofer-Inst. for Integrated Circuits, Dresden, Germany
C. Clauß , Fraunhofer-Inst. for Integrated Circuits, Dresden, Germany
W. Wünsche , Fraunhofer-Inst. for Integrated Circuits, Dresden, Germany
F. Winkler , Fraunhofer-Inst. for Integrated Circuits, Dresden, Germany
pp. 113

Modeling and Simulation of Electromechanical Transducers in Microsystems Using an Analogue Hardware Description Language (Abstract)

M. Laudon , Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
H.P. Amann , Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
P. Renaud , Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
F. Pellandini , Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
B. Romanowicz , Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
A. Boegli , Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
V. Moser , Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
P. Lerch , Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
pp. 119
Session 3A: Software Generation for Embedded Processors

Delay Management for Programmable Video Signal Processors (Abstract)

G. Essink , Philips Res., Eindhoven, Netherlands
M.L.G. Smeets , Philips Res., Eindhoven, Netherlands
E.H.L. Aarts , Philips Res., Eindhoven, Netherlands
E.A. de Kock , Philips Res., Eindhoven, Netherlands
pp. 126

Hierarchical Scheduling and Allocation of Multirate Systems on Heterogeneous Multiprocessors (Abstract)

Yanbing Li , Dept. of Electr. Eng., Princeton University, NJ, USA
Wayne Wolf , Dept. of Electr. Eng., Princeton University, NJ, USA
pp. 134

Retargetable Generation of Code Selectors from HDL Processor Models (Abstract)

Peter Marwedel , University of Dortmund, Dortmund, Germany
Rainer Leupers , University of Dortmund, Dortmund, Germany
pp. 140
Session 3B: Register Transfer Level Test Synthesis

An RTL Methodology to Enable Low Overhead Combinational Testing (Abstract)

Subhrajit Bhattacharya , C&C Res. Labs., NEC USA, Princeton, NJ, USA
Sujit Dey , C&C Res. Labs., NEC USA, Princeton, NJ, USA
Bhaskar Sengupta , C&C Res. Labs., NEC USA, Princeton, NJ, USA
pp. 146

A Controller Testability Analysis and Enhancement Technique (Abstract)

Zebo Peng , Dept. of Comp. and Info. Sci., Link?ping University, Link?ping, Sweden
Xinli Gu , Synopsys, Inc., Mountain View, CA, USA
Erik Larsson , Dept. of Comp. and Info. Sci., Link?ping University, Link?ping, Sweden
Krzysztof Kuchinski , Dept. of Comp. and Info. Sci., Link?ping University, Link?ping, Sweden
pp. 153

Analyzing Testability from Behavioral to RT Level (Abstract)

B. Rouzeyre , Lab. d'Inf., de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, Franc
R. Pires , Lab. d'Inf., de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, Franc
M.L. Flottes , Lab. d'Inf., de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, Franc
pp. 158
Session 3C: BDD's and Formal Verification

Fast and Efficient Construction of BDDs by Reordering Based Synthesis (Abstract)

A. Hett , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
R. Drechsler , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
B. Becker , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 168

Verification and Synthesis of Counters Based on Symbolic Techniques (Abstract)

G. Cabodi , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Camurati , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
L. Lavagno , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
S. Quer , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 176

Using MTBDDs for Discrete Timed Symbolic Model Checking (Abstract)

T. Kropf , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
J. Ruf , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 182
Session 3D: Microsystems Design II

Analysis of 3D Conjugate Heat Transfers in Electronics (Abstract)

B. Desaunettes , Epsilon Ingenierie, Labege, France
J.P. Fradin , Epsilon Ingenierie, Labege, France
L. Molla , Epsilon Ingenierie, Labege, France
pp. 190

Smart Sensor System Application: An Integrated Compass (Abstract)

G. Diemel , MESA Res. Inst., Twente Univ., Enschede, Netherlands
H.G. Kerkhoff , MESA Res. Inst., Twente Univ., Enschede, Netherlands
R.J.W.T. Tangelder , MESA Res. Inst., Twente Univ., Enschede, Netherlands
pp. 195

Automatic Transfer of Parametric FEM Models into CAD-Layout Formats for Top-Down Design of Microsystems (Abstract)

D. David , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Lang , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 200
Session 4A: Panel P3
Session 4B: High Performance Architectures for Multimedia and Communication ASICs

Design and Implementation of a Coprocessor for Cryptography Applications (Abstract)

Javier Moran , Universidad Polit?cnica de Madrid
Ander Royo , Universidad Polit?cnica de Madrid
Juan Carlos Lopez , Universidad Polit?cnica de Madrid
pp. 213

On the Way to the 2.5 Gbits/s ATM Network ATM Multiplexer Demultiplexer ASIC (Abstract)

L.A. Merayo , Telefonica Investigacion y Desarrollo, Madrid, Spain
J.C. Díaz , Telefonica Investigacion y Desarrollo, Madrid, Spain
J.L. Conesa , Telefonica Investigacion y Desarrollo, Madrid, Spain
C. Santos , Telefonica Investigacion y Desarrollo, Madrid, Spain
J. Riesco , Telefonica Investigacion y Desarrollo, Madrid, Spain
E. Juárez , Telefonica Investigacion y Desarrollo, Madrid, Spain
pp. 218
Session 4C: Decision Diagrams and Diagnosis

Solving Graph Optimization Problems with ZBDDs (Abstract)

O. Coudert , Synopsys Inc., Mountain View, CA, USA
pp. 224

Minimizing ROBDD Sizes of Incompletely Specified Boolean Functions by Exploiting Strong Symmetries (Abstract)

S. Melchior , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
G. Hotz , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
C. Scholl , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
P. Molitor , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 229

Connection Errors Location and Correction in Combinational Circuits (Abstract)

Ayman Wahba , Joseph Fourier University
Dominique Borrione , Joseph Fourier University
pp. 235
Session 4D: Performance Modeling

Shaping a VLSI Wire to Minimize Elmore Delay (Abstract)

J.P. Fishburn , Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA
pp. 244

Inductance Analysis of On-Chip Interconnects (Abstract)

U. Ghoshal , Res. Lab., IBM Corp., Austin, TX, USA
S. Kundu , Res. Lab., IBM Corp., Austin, TX, USA
pp. 252

Cartesian Multipole Based Numerical Integration for 3D Capacitance Extraction (Abstract)

N.P. van der Meijs , Delft Univ. of Technol., Netherlands
U. Geigenmüller , Delft Univ. of Technol., Netherlands
pp. 256
Session 5A: Hot Topic HT1
Session 5B: Progress in IDDQ Test Technology

CCII+ Current Conveyor Based BIC Monitor for IDDQ Testing of Complex CMOS Circuits (Abstract)

H. Manhaeve , Dept. of Microelectron., Slovak Tech. Univ., Bratislava, Slovakia
V. Stopjaková , Dept. of Microelectron., Slovak Tech. Univ., Bratislava, Slovakia
pp. 266

Deep Sub-Micron IDDQ Testing: Issues and Solutions (Abstract)

M. Sachdev , Philips Res. Lab., Eindhoven, Netherlands
pp. 271

A Production-Oriented Measurement Method for Fast and Exhaustive Iddq Tests (Abstract)

B. Laquai , IMS, Stuttgart, Germany
H. Richter , IMS, Stuttgart, Germany
H. Werkmann , IMS, Stuttgart, Germany
pp. 279
Session 5C: Architecture Exploration

Library Mapping for Memories (Abstract)

Pradip K. Jha , IBM East Fishkill Facility
Nikil D. Dutt , University of California at Irvine
pp. 288

Architectural Exploration and Optimization for Counter Based Hardware Address Generation (Abstract)

M. Miranda , IMEC, Leuven, Belgium
F. Catthoor , IMEC, Leuven, Belgium
M. Kaspar , IMEC, Leuven, Belgium
H. de Man , IMEC, Leuven, Belgium
pp. 293

RTL Synthesis with Physical and Controller Information (Abstract)

Min Xu , University of California, Irvine
Fadi Kurdahi , University of California, Irvine
pp. 299
Session 5D: Layout Design

Layout Design (PDF)

pp. null

Two-way partitioning based on direction vector (Abstract)

C.M. Kyung , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
K.S. Seong , Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
pp. 306

Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic (Abstract)

C. Sechen , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Le-Chin Eugene Liu , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 311

A gridless multi-layer router for standard cell circuits using CTM cells (Abstract)

C. Sechen , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Hsiao-Ping Tseng , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 319
Session 6A: Hot Topic HT2
Session 6B: Testability Solutions for Regular Structures

Fault-secure shifter design: results and implementations (Abstract)

Y. Zorian , TIMA, Grenoble, France
R.O. Duarte , TIMA, Grenoble, France
H. Bederr , TIMA, Grenoble, France
M. Nicolaidis , TIMA, Grenoble, France
pp. 335
Session 6C: Data Converter Test Issues

Efficient and accurate testing of analog-to-digital converters using oscillation-test method (Abstract)

B. Kaminska , Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada
K. Arabi , Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada
pp. 348

Built-in self-test methodology for A/D converters (Abstract)

R. de Vries , Philips Res. Lab., Eindhoven, Netherlands
P.P.L. Regtien , Philips Res. Lab., Eindhoven, Netherlands
T. Zwemstra , Philips Res. Lab., Eindhoven, Netherlands
E.M.J.G. Bruls , Philips Res. Lab., Eindhoven, Netherlands
pp. 353

Reconfigurable data converter as a building block for mixed-signal test (Abstract)

E.K.F. Lee , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 359
Session 7A: Hot Topic HT3
Session 7B: Extensions and Acceleration of Discrete Event Simulation

VHDL extensions for complex transmission line simulation (Abstract)

S. Ghosh , Div. of Eng., Brown Univ., Providence, RI, USA
P. Walker , Div. of Eng., Brown Univ., Providence, RI, USA
pp. 368

Acceleration of Behavioral Simulation on Simulation Specific Machines (Abstract)

Satoshi Kowatari , Fuhitsu Limited
Fumiyasu Hirose , Fuhitsu Limited
Shintaro Shimogori , Fuhitsu Limited
Hiroshi Nagai , Fuhitsu Limited
Minoru Shoji , Fuhitsu Limited
pp. 373

Exploiting temporal independence in distributed preemptive circuit simulation (Abstract)

S. Ghosh , Div. of Eng., Brown Univ., Providence, RI, USA
P. Walker , Div. of Eng., Brown Univ., Providence, RI, USA
pp. 378
Session 7C: Analog Design and Layout Tools

Analogue layout generation by World Wide Web server-based agents (Abstract)

K. Shi , Electron. Eng. Labs., Kent Univ., Canterbury, UK
D. Nalbantis , Electron. Eng. Labs., Kent Univ., Canterbury, UK
L.T. Walczowski , Electron. Eng. Labs., Kent Univ., Canterbury, UK
W.A.J. Waller , Electron. Eng. Labs., Kent Univ., Canterbury, UK
pp. 384

A Performance-Driven Placement Algorithm with Simultaneous Place&Route Optimization for Analog IC's (Abstract)

Jose M. Quintana , Centro Nacional de Microelectronica.
Adoracion Rueda , Centro Nacional de Microelectronica.
Jose L. Huertas , Centro Nacional de Microelectronica.
Juan A. Prieto , Centro Nacional de Microelectronica.
pp. 389

An Algorithm for Numerical Reference Generation in Symbolic Analysis of Large Analog Circuits (Abstract)

Francisco V. Fernandez , Centro Nacional de Microelectronica
Angel Rodriguez-Vazque. , Centro Nacional de Microelectronica
Ignacio Garcia-Vargas , Centro Nacional de Microelectronica
Mariano Galan , Centro Nacional de Microelectronica
pp. 395
Session 8A: Embedded Tutorial
Session 8B: Power Modeling and Estimation

Adaptive least mean square behavioral power modeling (Abstract)

G. De Micheli , DEIS, Bologna Univ., Italy
A. Bogliolo , DEIS, Bologna Univ., Italy
L. Benini , DEIS, Bologna Univ., Italy
pp. 404

Fast power loss calculation for digital static CMOS circuits (Abstract)

L. Jones , Acad. of Sci., Moscow, Russia
D. Blaauw , Acad. of Sci., Moscow, Russia
G. Vijayan , Acad. of Sci., Moscow, Russia
S. Gavrilov , Acad. of Sci., Moscow, Russia
S. Rusakov , Acad. of Sci., Moscow, Russia
A. Glebov , Acad. of Sci., Moscow, Russia
pp. 411

Monte-Carlo Approach for Power Estimation in Sequential Circuits (Abstract)

Farid N. Najm , University of Illinois at Urbana-Champaign
Vikram Saxena , Synopsys Inc.
Ibrahim Hajj , University of Illinois at Urbana-Champaign
pp. 416
Session 8C: Formal Methods in Synthesis and Verification

Hybrid symbolic-explicit techniques for the graph coloring problem (Abstract)

F. Corno , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
S. Chiusano , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 422

A constructive approach towards correctness of synthesis-application within retiming (Abstract)

R. Kumar , Inst. for Circuit Design & Fault Tolerance, Karlsruhe Univ., Germany
C. Blumenrohr , Inst. for Circuit Design & Fault Tolerance, Karlsruhe Univ., Germany
D. Eisenbiegler , Inst. for Circuit Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 427

A symbolic core approach to the formal verification of integrated mixed-mode applications (Abstract)

S. Hendriex , Katholieke Univ., Leuven, Heverlee, Belgium
L. Claesen , Katholieke Univ., Leuven, Heverlee, Belgium
pp. 432
Session 9A: Panel P2
Session 9B: Concurrent Checking

A Novel Methodology for Designing TSC Networks Based on the Parity Bit Code (Abstract)

Fabio Salice , Politecnico di Milano
Cristiana Bolchini , Politecnico di Milano
Donatella Sciuto , Politecnico di Milano
pp. 440

Testing scheme for IC's clocks (Abstract)

M. Favalli , DEIS, Bologna Univ., Italy
C. Metra , DEIS, Bologna Univ., Italy
pp. 445
Session 9C: New Ideas in Scheduling

Cone Based Clustering for List Scheduling Algorithms (Abstract)

Sriram Govindarajan , University of Cincinnati
Ranga Vemuri , University of Cincinnati
pp. 456

Register Synthesis for Speculative Computation (Abstract)

Dirk Herrmann , Technical University of Braunschweig
Rolf Ernst , Technical University of Braunschweig
pp. 463

Multidimensional periodic scheduling: a solution approach (Abstract)

J.L. van Meerbergen , Philips Res. Lab., Eindhoven, Netherlands
P.E.R. Lippens , Philips Res. Lab., Eindhoven, Netherlands
W.F.J. Verhaegh , Philips Res. Lab., Eindhoven, Netherlands
E.H.L. Aarts , Philips Res. Lab., Eindhoven, Netherlands
pp. 468
Session 10A: System Level Design Representation and Transformation

PCC: a modeling technique for mixed control/data flow systems (Abstract)

R. Schoenen , Aachen Univ. of Technol., Germany
T. Grotker , Aachen Univ. of Technol., Germany
H. Meyr , Aachen Univ. of Technol., Germany
pp. 482

Procedure cloning: a transformation for improved system-level functional partitioning (Abstract)

F. Vahid , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
pp. 487
Session 10B: Diagnosis and Test Generation

A fault diagnosis methodology for the UltraSPARC/sup TM/-I microprocessor (Abstract)

M.E. Levitt , Sun Microsyst. Inc., Mountain View, CA, USA
S. Bozorgui-Nesbat , Sun Microsyst. Inc., Mountain View, CA, USA
S. Narayanan , Sun Microsyst. Inc., Mountain View, CA, USA
R.P. Kunda , Sun Microsyst. Inc., Mountain View, CA, USA
R. Srinivasan , Sun Microsyst. Inc., Mountain View, CA, USA
pp. 494

Improved diagnosis of realistic interconnect shorts (Abstract)

P.Y.K. Cheung , Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
J.T. de Sousa , Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
pp. 501

On improving genetic optimization based test generation (Abstract)

I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, US
S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, US
pp. 506
Session 10C: Logic Synthesis for Low Power

Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks (Abstract)

G. De Micheli , Comput. Syst. Lab., Stanford Univ., CA, USA
L. Benini , Comput. Syst. Lab., Stanford Univ., CA, USA
R. Scarsi , Comput. Syst. Lab., Stanford Univ., CA, USA
M. Poncino , Comput. Syst. Lab., Stanford Univ., CA, USA
E. Macii , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 514

Low power FSM design using Huffman-style encoding (Abstract)

A. Tyagi , Intel Corp., Folsom, CA, USA
P. Surti , Intel Corp., Folsom, CA, USA
L.F. Chao , Intel Corp., Folsom, CA, USA
pp. 521
Session 11A: System Design Methodologies

Practical concurrent ASIC and system design and verification (Abstract)

I. Gibson , Canon Inf. Syst. Res., North Ryde, NSW, Australia
C. Amies , Canon Inf. Syst. Res., North Ryde, NSW, Australia
pp. 532
Session 11B: Testability at Different Abstraction Levels

Testability of 2-level AND/EXOR circuits (Abstract)

R. Drechsler , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
J. Hartmann , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
H. Schafer , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
B. Becker , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
H. Hengster , Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 548

On the use of reset to increase the testability of interconnected finite-state machines (Abstract)

S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 554

A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs (Abstract)

P. Prinetto , Politecnico di Torino, Italy
M. Rebaudengo , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
A. Benso , Politecnico di Torino, Italy
R. Ubar , Politecnico di Torino, Italy
pp. 560
Session 11C: Hardware and Software Tools for Analog and Mixed-Signal Test

On-chip analog output response compaction (Abstract)

F. Azais , Lab. d'Inf., LIRMM, Montpellier, France
M. Renovell , Lab. d'Inf., LIRMM, Montpellier, France
Y. Bertrand , Lab. d'Inf., LIRMM, Montpellier, France
pp. 568

Compact structural test generation for analog macros (Abstract)

H. Kerkhoff , MESA Res. Inst., Twente Univ., Enschede, Netherlands
V. Kaal , MESA Res. Inst., Twente Univ., Enschede, Netherlands
pp. 581
Session 11D: Power Estimation and Modeling

Accurate high level datapath power estimation (Abstract)

J.E. Crenshaw , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
M. Sarrafzadeh , Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 590

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model (Abstract)

J. Figueras , Univ. Politecnica de Catalunya, Barcelona, Spain
S. Manich , Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 597

Internal power modelling and minimization in CMOS inverters (Abstract)

S. Turgis , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
J.M. Portal , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
J.M. Daga , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
D. Auvergne , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 603
Poster Session

A new field programmable system-on-a-chip for mixed signal integration (PDF)

C. Horton , SIDSA, Parque Technol., Madrid, Spain
J.M. Insenser , SIDSA, Parque Technol., Madrid, Spain
J. Faura , SIDSA, Parque Technol., Madrid, Spain
B. Krah , SIDSA, Parque Technol., Madrid, Spain
J. Cabestany , SIDSA, Parque Technol., Madrid, Spain
M.A. Aguirre , SIDSA, Parque Technol., Madrid, Spain
pp. 610

PROPHID: a data-driven multi-processor architecture for high-performance DSP (PDF)

J.L. van Meerbergen , Philips Res. Lab., Eindhoven, Netherlands
J.A.J. Leijten , Philips Res. Lab., Eindhoven, Netherlands
A.H. Timmer , Philips Res. Lab., Eindhoven, Netherlands
J.A.G. Jess , Philips Res. Lab., Eindhoven, Netherlands
pp. 611

ReCode: the design and re-design of the instruction codes for embedded instruction-set processors (PDF)

C. Liem , Lab. TIMA, INPG, Grenoble, France
P. Paulin , Lab. TIMA, INPG, Grenoble, France
A. Jerraya , Lab. TIMA, INPG, Grenoble, France
pp. 612

A real-time smart sensor system for visual motion estimation (PDF)

L. Peters , German Nat. Res. Center for Comput. Sci., St. Augustin, Germany
T. Rowekamp , German Nat. Res. Center for Comput. Sci., St. Augustin, Germany
pp. 613

Test synthesis for DC test of switched-capacitors circuits (PDF)

H. Ihs , Lab. d'Inf., Robotique et de Micro-electronique, Montpellier, France
C. Dufaza , Lab. d'Inf., Robotique et de Micro-electronique, Montpellier, France
pp. 616

SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells (PDF)

A. Poppe , Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
V. Szekely , Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
A. Pahi , Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
M. Rencz , Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
A. Csendes , Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
pp. 617

Design of Oscillation-Based Test Structures for Active RC Filters (PDF)

Franc Novak , Jozef Stefan Institute
Srecko Macek , Jozef Stefan Institute
Marina Santo Zarnik , Hipot Hybrid
pp. 618

Optimal Scheduling for Fast Systolic Array Implementations (PDF)

I. Ozimek , Institute Jozef Stefan
R. Verlic , Institute Jozef Stefan
J. Tasic , University of Ljubljana
pp. 620

Scheduling using mixed arithmetic: an ILP formulation (PDF)

A. Mignotte , Ecole Normale Superieure de Lyon, France
O. Peyran , Ecole Normale Superieure de Lyon, France
pp. 621

Performance verification using partial evaluation and interval analysis (PDF)

R. Vemuri , Dept. of Electron. Comput., Cincinnati Univ., OH, USA
W. Bradley , Dept. of Electron. Comput., Cincinnati Univ., OH, USA
J. Walrath , Dept. of Electron. Comput., Cincinnati Univ., OH, USA
pp. 622

Design and Verification of the Sequential Systems Automata Using Temporal Logic Specifications (PDF)

A. Ursu , Technical University of Moldova
G. Gruita , Technical University of Moldova
S. Zaporojan , Technical University of Moldova
pp. 623

Application independent module generation in analog layouts (PDF)

U. Kleine , Otto-von-Guericke-Univ., Magdeburg, Germany
M. Wolf , Otto-von-Guericke-Univ., Magdeburg, Germany
pp. 624

A scheme for multiple on-chip signature checking for embedded SRAMs (PDF)

A. Kumar , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India
M.F. Abdulla , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India
C.P. Ravikumar , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India
pp. 625

Design of Partially Parallel Scan Chain (PDF)

Yoshinobu Higami , Osaka University
Kozo Kinoshita , Osaka University
pp. 626

March LA: a test for linked memory faults (PDF)

A.J. van de Goor , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
G.N. Gaydadjiev , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
V.G. Mikitjuk , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
V.N. Yarmolik , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 627

The input pattern fault model and its application (PDF)

J.P. Hayes , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.D. Blanton , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 628

A monolithic off-chip IDDQ monitor (PDF)

B. Straka , Tech. Univ. of Brno, Czech Republic
H. Manhaeve , Tech. Univ. of Brno, Czech Republic
M. Svajda , Tech. Univ. of Brno, Czech Republic
pp. 629

Author Index (PDF)

pp. 631
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