The Community for Technology Leaders
European Design and Test Conference (1996)
Paris, FRANCE
Mar. 11, 1996 to Mar. 14, 1996
ISSN: 1066-1409
ISBN: 0-8186-7423-7
TABLE OF CONTENTS

Keynote Speakers (PDF)

pp. xviii

Welcome Message (PDF)

pp. xxiv

Tutorials (PDF)

pp. xxvi

Best Paper Award (PDF)

pp. xxx

List of Reviewers (PDF)

pp. xxxi
Session 1A: Formal Verification

K*BMDs: A New Data Structure for Verification (Abstract)

Rolf Drechsler , Institute of Computer Science, Albert-Ludwigs-University
Bernd Becker , Institute of Computer Science, Albert-Ludwigs-University
Stefan Ruppertz , Department of Computer Science, J.W. Goethe-University, Frankfurt am Main, Germany
pp. 2

Exploiting Functional Dependencies in Finite State Machine Verification (Abstract)

J.A.G. Jess , Eindhoven University of Technology
C.A.J. Van Eijk , Eindhoven University of Technology
pp. 9

An Efficient Algorithm for Real-Time Symbolic Model Checking (Abstract)

J. Gerlach , Lehrstuhl Technische Informatik Universitaet Tuebingen
Th. Kropf , Institut fuer Rechnerentwurf und Fehlertoleranz Universitaet Karlsruhe,
J. Froessl , Institut fuer Rechnerentwurf und Fehlertoleranz Universitaet Karlsruhe,
pp. 15
Session 1B: System Design for Digital Broadband Telecom: Trends and System Design Challenges

Design challenges of high speed ATM communication ASICs (Abstract)

J.L. Conesa , Microelectron. Div., Telefonica I+D, Madrid, Spain
pp. 27
Session 1C: BIST Pattern Generation

Multiplicative Window Generators of Pseudo-random Test Vectors (Abstract)

Janusz Rajski , Mentor Graphics Corporation
Jerzy Tyszer , The Franco-Polish School of New Information and Communication Technologies
pp. 42
Session 2A: New Domains in High-Level Synthesis

High-level synthesis of gracefully degradable ASICs (Abstract)

A. Orailoglu , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
Wah Chan , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 50

High-Level Synthesis of Recoverable Microarchitectures (Abstract)

Fadi J. Kurdahi , University of California, Irvine
Douglas M. Blough , University of California, Irvine
Seong Y. Ohm , University of California, Irvine
pp. 55

Reducing Address Bus Transitions for Low Power Memory Mapping (Abstract)

Preeti R. Panda , University of California, Irvine
Nikil D. Dutt , University of California, Irvine
pp. 63
Session 2C: Fault Analysis and Test Quality

Assessing the Quality Level of Digital CMOS IC's under the Hypothesis of Non-Uniform Distribution of Fault Probabilities (Abstract)

C. Marzocca , Dipartimento di Elettrotecnica ed Elettronica Politecnico di Bari Via Orabona 4, 70125 Bari , Italy
S. Martino , Tecnopolis CSATA Novus Ortus Laboratorio di Microelettronica Strada Prov. Casamassima km. 3 70010 Valenzano - Bari, Italy
F. Corsi , Dipartimento di Elettrotecnica ed Elettronica Politecnico di Bari Via Orabona 4, 70125 Bari , Italy
pp. 72

DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits (Abstract)

C. Landrault , UMR 9928 University Montpellier II / CNRS
S. Pravossoudovitch , UMR 9928 University Montpellier II / CNRS
P. Cavallera , UMR 9928 University Montpellier II / CNRS
P. Girard , UMR 9928 University Montpellier II / CNRS
pp. 79
Session 3A: Code Generation

A Graph Based Processor Model for Retargetable Code Generation (Abstract)

Gert Goossens , IMEC (VSDM) Kapeldreef 75, B-3001 Leuven, Belgium
Hugo de Man , IMEC (VSDM) Kapeldreef 75, B-3001 Leuven, Belgium
Werner Geurts , IMEC (VSDM) Kapeldreef 75, B-3001 Leuven, Belgium
Dirk Lanneer , IMEC (VSDM) Kapeldreef 75, B-3001 Leuven, Belgium
Johan van Praet , IMEC (VSDM) Kapeldreef 75, B-3001 Leuven, Belgium
pp. 102

Operation Serializability for Embedded Systems (Abstract)

Rajesh K. Gupta , University of Illinois, Urbana-Champaign
pp. 108
Session 3B: IDDQ: You Heard the Hype, But What's Really Coming?

IDDQ: you heard the hype, but what's really coming? (Abstract)

K. Baker , Philips Res. Lab., Eindhoven, Netherlands
pp. 116
Session 3C: Test and BIST Beyond Chips

Decentralized BIST for 1149.1 and 1149.5 Based Interconnects (Abstract)

Yuan-Tzu Ting , Chung-shan Institute of Science & Technology
Shyh-Jye Jou , National Central University
Chauchin Su , National Central University
pp. 120

Test Structures on MCM Active Substrate: Is it worthwhile? (Abstract)

J. Oliver , IMB-CNM (CSIC), University Autonoma of Barcelona
H. Kerkhoff , MESA Institute, University of Twente
pp. 126

Relay Propagation Scheme for Testing of MCMs on Large Area Substrates (Abstract)

A. Chatterjee , Georgia Institute of Technology
K. Sasidhar , Georgia Institute of Technology
Y. Zorian , AT&T Bell Laboratories
pp. 131
Session 4A: Transformations and Estimations

An evolution programming approach on multiple behaviors for the design of application specific programmable processors (Abstract)

C.A. Papachristou , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
Wei Zhao , Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
pp. 144

Area and Timing Estimation for Lookup Table Based FPGAs (Abstract)

Min Xu , University of California, Irvine
Fadi Kurdahi , University of California, Irvine
pp. 151
Session 4B: FPGA Placement and Routing

Detailed-Routability of FPGAs with Extremal Switch-Block Structures (Abstract)

Y. Takashima , Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech. 2-12-1 Ookayama, Meguro-ku, Tokyo 152, Japan
A. Takahashi , Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech. 2-12-1 Ookayama, Meguro-ku, Tokyo 152, Japan
Y. Kajitani , Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech. 2-12-1 Ookayama, Meguro-ku, Tokyo 152, Japan
pp. 160
Session 4C: Self-Test Methodologies

Built-in self test architectures for multistage interconnection networks (Abstract)

E. Bernard , OEN TN ETD3, Siemens AG, Munich, Germany
S. Simon , OEN TN ETD3, Siemens AG, Munich, Germany
J.A. Nossek , OEN TN ETD3, Siemens AG, Munich, Germany
pp. 176

Designing Self-Testable Multi-Chip Modules (Abstract)

Hakim Bederr , AT&T Bell Laboratories
Yervant Zorian , AT&T Bell Laboratories
pp. 181

Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations (Abstract)

J. Figueras , UPC, Diagonal 647
S. Manich , UPC, Diagonal 647
M. Nicolaidis , Reliable Integrated Systems Group
pp. 186
Session 4D: Emerging Design Techniques

Power Optimization of Delay Constrained CMOS Bus Drivers (Abstract)

J. Figueras , Universitat Politecnica de Catalunya
S. Caufape , Universitat Politecnica de Catalunya
pp. 205
Session 5A: Low Power Design

Optimizing CMOS Circuits for Low Power Using Transistor Reordering (Abstract)

Jordi Cortadella , Universitat Politecnica de Catalunya
Enric Musoll , Universitat Politecnica de Catalunya
pp. 219

Design and selection of buffers for minimum power-delay product (Abstract)

D. Auvergne , Lab. d'Inf. de Robotique et de Mictroelectron., CNRS, Montpellier, France
S. Turgis , Lab. d'Inf. de Robotique et de Mictroelectron., CNRS, Montpellier, France
N. Azemard , Lab. d'Inf. de Robotique et de Mictroelectron., CNRS, Montpellier, France
pp. 224
Session 5B: Performance-Driven Routing

An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion (Abstract)

Y. P. Chen , The University of Texas at Austin
D. F. Wong , The University of Texas at Austin
pp. 230

A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning (Abstract)

Hiroaki Matsuda , NTT LSI Laboratories
Akira Onozawa , NTT LSI Laboratories
Hidenori Sato , NTT LSI Laboratories
pp. 237

Constructing Minimal Spanning/Steiner Trees with Bounded Path Length (Abstract)

Massoud Pedram , University of Southern California
Iksoo Pyo , Intel Corportation
Jaewon Oh , University of Southern California
pp. 244
Session 5D: Test Generation for Mixed-Signal Circuits

FLAMES: A Fuzzy Logic ATMS and Model-based Expert System for Analog Diagnosis (Abstract)

M. Marzouki , TIMA Laboratory, 46 avenue Felix Viallet
M.H. Touati , TIMA Laboratory, 46 avenue Felix Viallet
F. Mohamed , TIMA Laboratory, 46 avenue Felix Viallet
pp. 259

Evaluation of iDD/vOUT Cross-Correlation for Mixed Current/Voltage Testing of Analogue and Mixed-Signal Circuits (Abstract)

J. Silva Matos , Faculdade de Engenharia da Universidade do Porto - INESC
J. Machado da Silva , Faculdade de Engenharia da Universidade do Porto - INESC
pp. 264
Session 6A: Heterogeneous System Modelling and Design

Model Refinement for Hardware-Software Codesign (Abstract)

Daniel D. Gajski , Department of Information and Computer Science University of California, Irvine
Smita Bakshi , Department of Information and Computer Science University of California, Irvine
Jie Gong , Department of Information and Computer Science University of California, Irvine
pp. 270

Thread-based software synthesis for embedded system design (Abstract)

Kiyoung Choi , Dept. of Electron. Eng., Seoul Nat. Univ., South Korea
Youngsoo Shin , Dept. of Electron. Eng., Seoul Nat. Univ., South Korea
pp. 282
Session 6B: Analysis in Digital Circuit Design

Bounding Switching Activity in CMOS Circuits Using Constraint Resolution (Abstract)

S. Shenoy , Dept. of EE, McGill University
J. Zejda , Dep. I.R.O., Universite de Montreal
E. Cerny , Dep. I.R.O., Universite de Montreal
N. C. Rumin , Dept. of EE, McGill University
pp. 294
Session 6D: High Speed Signal Processing

VLSI Architecture for Motion Estimation using the Block-Matching Algorithm (Abstract)

Matias J. Garrido , Technical University of Madrid, Spain
Cesar Sanz , Technical University of Madrid, Spain
Juan M. Meneses , Technical University of Madrid, Spain
pp. 310

High Rate Soft Output Viterbi Decoder (Abstract)

Emmanuel Casseau , Integrated Circuits for Telecommunications Laboratory
Eric Luthi , Integrated Circuits for Telecommunications Laboratory
pp. 315
Session 7A: Sequential Logic Synthesis

Constructive Analysis of Cyclic Circuits (Abstract)

Herve Touati , Paris Research Laboratory Digital Equipment Corporation
Gerard Berry , Ecole des Mines
Thomas R. Shiple , University of California, Berkeley
pp. 328

Sequential Permissible Functions and their Application to Circuit Optimization (Abstract)

Malgorzata Marek-Sadowska , Univ. of California, Santa Barbara
Chih-chang Lin , Univ. of California, Santa Barbara
Mike Tien-Chien Lee , Fujitsu Laboratories of America
Kuang-Chien Chen , Fujitsu Laboratories of America
pp. 334

Structural Methods for the Synthesis of Speed-Independent Circuits (Abstract)

Oriol Roig , Universitat Politecnica de Catalunya
Jordi Cortadella , Universitat Politecnica de Catalunya
Enric Pastor , Universitat Politecnica de Catalunya
Alex Kondratyev , The university of Aizu
pp. 340
Session 7B: From High Level Verification to (Low Level) Extraction

Observable Time Windows: Verifying the Results of High-Level Synthesis (Abstract)

Salil Raje , Northwestern University
Reinaldo A. Bergamaschi , IBM T. J. Watson Research Center
pp. 350

PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor (Abstract)

Wolfgang Meier , Siemens AG, Corporate Research and Development
Frank Scherber , University of Hanover
Erich Barke , University of Hanover
pp. 357

Including Higher-Order Moments of RC Interconnections in Layout-to-Circuit Extraction (Abstract)

N.P. van der Meijs , Delft University of Technology
P.J.H. Elias , Delft University of Technology
pp. 362
Session 7C: Sequential Test Generation

Alternating Strategies for Sequential Circuit ATPG (Abstract)

Janak H. Patel , Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL 61801
Michael S. Hsiao , Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL 61801
Elizabeth M. Rudnick , Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL 61801
pp. 368

Advanced Techniques for GA-based sequential ATPGs (Abstract)

R. Mosca , CSP (Centro Supercalcolo Piemonte)
F. Corno , Politecnico di Torino, Dip. Automatica e Informatica
M. Sonza Reorda , Politecnico di Torino, Dip. Automatica e Informatica
M. Rebaudengo , Politecnico di Torino, Dip. Automatica e Informatica
P. Prinetto , Politecnico di Torino, Dip. Automatica e Informatica
pp. 375

On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem (Abstract)

Sudhakar M. Reddy , Electrical and Computer Engineering Department University of Iowa
Irith Pomeranz , Electrical and Computer Engineering Department University of Iowa
pp. 380
Session 7D: Module Generators

A Novel Analog Module Generator Environment (Abstract)

M. Wolf , Otto-von-Guericke-Universitaet Magdeburg
B. J. Hosticka , Fraunhofer Institute of Microelectronic Circuits and Systems
U. Kleine , Otto-von-Guericke-Universitaet Magdeburg
pp. 388

XPRESS: A Cell Layout Generator with Integrated Transistor Folding (Abstract)

Avaneendra Gupta , avigupta@eecs.umich.edu
Siang-Chun The , sthe@scdt.intel.com
John P. Hayes , jhayes@eecs.umich.edu
pp. 393
Session 8A: Logic Synthesis

Rapid Gate Matching with Don't Cares (Abstract)

A.-M. Trullemans , UCL-Laboratoire de MicroElectronique
Q. Zhang , UCL-Laboratoire de MicroElectronique
pp. 407

An Implicit Algorithm for Support Minimization during Functional Decomposition (Abstract)

Klaus Eckl , Institute of Electronic Design Automation Technical University of Munich
Christian Legl , Institute of Electronic Design Automation Technical University of Munich
Bernd Wurth , Institute of Electronic Design Automation Technical University of Munich
pp. 412
Session 8B: Memory Testing

Towards a Uniform Notation for Memory Tests (Abstract)

Ivo Schanstra , Delft University of Technology
Aad Offerman , Delft University of Technology
Ad J. van de Goor , Delft University of Technology
pp. 420

RAM Testing Algorithm for Detection Linked Coupling Faults (Abstract)

V.N. Yarmolik , Byelorussian State University of Informatics and Radioelectronics
V.G. Mikitjuk , Byelorussian State University of Informatics and Radioelectronics
A.J. van de Goor , Delft University of Technology
pp. 435
Session 8C: Design Environments and CAD Tools for Microsystems Design

High level CAD melds microsystems with foundries (Abstract)

J.M. Karam , CMP, Grenoble, France
M. Bauge , CMP, Grenoble, France
B. Courtois , CMP, Grenoble, France
pp. 442

A conceptual design environment for micromechanisms (Abstract)

N. Shibaike , Res. into Artifacts, Tokyo Univ., Japan
S. Yoshimura , Res. into Artifacts, Tokyo Univ., Japan
S. Burgess , Res. into Artifacts, Tokyo Univ., Japan
N. Nakajima , Res. into Artifacts, Tokyo Univ., Japan
T. Kiriyama , Res. into Artifacts, Tokyo Univ., Japan
D. Moore , Res. into Artifacts, Tokyo Univ., Japan
pp. 448

SUZANA: A 3D CAD Tool for Anisotropically Etched Silicon Microstructures (Abstract)

S. Büttgenbach , Institute for Microtechnology Technical University of Braunschweig D-38106 Braunschweig, Germany
O. Than , Institute for Microtechnology Technical University of Braunschweig D-38106 Braunschweig, Germany
pp. 454
Session 9A: Partitioning in System Design

Recursive Bipartitioning of Signal Flow Graphs for Programmable Video Signal Processors (Abstract)

E.A. de Kock , Philips Research The Netherlands
E.H.L. Aarts , Philips Research The Netherlands
G. Essink , Philips Research The Netherlands
pp. 460

An Automatic Hardware-Software Partitioner Based on the Possibilistic Programming. (Abstract)

I. Karkowski , Delft University of Technology
R.H.J.M. Otten , Delft University of Technology
pp. 467

Hardware/Software Partitioning using Integer Programming (Abstract)

Ralf Niemann , University of Dortmund
Peter Marwedel , University of Dortmund
pp. 473
Session 9B: Synthesis and Testability

Partial Scan High-Level Synthesis (Abstract)

Victor Fernandez , Microelectronics Group. TEISA
Pablo Sanchez , Microelectronics Group. TEISA
pp. 481

Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability (Abstract)

Angela Krstic , University of California, Santa Barbara, CA 93106
Kwang-Ting Cheng , University of California, Santa Barbara, CA 93106
pp. 486

A Fast Optimal Robust Path Delay Fault Testable Adder (Abstract)

Rolf Krieger , J.W. Goethe-University
Rolf Drechsler , Albert-Ludwigs-University
Sudhakar M. Reddy , University of Iowa
Bernd Becker , Albert-Ludwigs-University
pp. 491
Session 9C: Novelties in Integrated System Design

A Memory-based Architecture for MPEG2 System Protocol LSIs (Abstract)

Makoto Endo , NTT LSI Laboratories
Jiro Naganuma , NTT LSI Laboratories
Haruo Wakabayashi , NTT LSI Laboratories
Minoru Inamori , NTT LSI Laboratories
pp. 500

Incorporating Multi-Chip Module Packaging Constraints into System Design (Abstract)

D. Scott Wills , Georgia Institute of Technology
Vivek Garg , Georgia Institute of Technology
Steve Lacy , Georgia Institute of Technology
Sudhakar Yalamanchili , Georgia Institute of Technology
Craig Ulmer , Georgia Institute of Technology
David E. Schimmel , Georgia Institute of Technology
Darrell Stogner , Georgia Institute of Technology
pp. 508

FORM: A Frame-Oriented Representation Method for Digital Telecommunication System Design (Abstract)

K. Yamada , NTT Optical Network Systems Laboratories
T. Miyazaki , NTT Optical Network Systems Laboratories
K. Shirakawa , NTT Optical Network Systems Laboratories
K. Hayashi , NTT Optical Network Systems Laboratories
K. Higuchi , NTT Optical Network Systems Laboratories
pp. 514
Session 10A: Modelling and Design Strategies for Microsystems Design

Defect-Oriented Experiments in Fault Modelling and Fault Simulation of Microsystem Components (Abstract)

Andreas Holubek , Fraunhofer-Institut fuer Integrierte Schaltungen
Wolfgang Vermeiren , Fraunhofer-Institut fuer Integrierte Schaltungen
Bernd Straube , Fraunhofer-Institut fuer Integrierte Schaltungen
pp. 522

Applied design and analysis of microsystems (Abstract)

K. Hofmann , TIMA, Grenoble, France
A. Poppe , TIMA, Grenoble, France
B. Courtois , TIMA, Grenoble, France
M. Rencz , TIMA, Grenoble, France
J.M. Karam , TIMA, Grenoble, France
M. Glesner , TIMA, Grenoble, France
V. Szekely , TIMA, Grenoble, France
pp. 528

Step by Step from Specification to Realization of an Electrochemical Microsystem (Abstract)

R. Rapp , Forschungszentrum Karlsruhe Institut fuer Angewandte Informatik
W. Jakob , Forschungszentrum Karlsruhe Institut fuer Angewandte Informatik
K. Lindemann , Forschungszentrum Karlsruhe Institut fuer Angewandte Informatik
W. Suess , Forschungszentrum Karlsruhe Institut fuer Angewandte Informatik
W. Hoffmann , Forschungszentrum Karlsruhe Institut fuer Angewandte Informatik
M. Gorges-Schleuter , Forschungszentrum Karlsruhe Institut fuer Angewandte Informatik
H. Eggert , Forschungszentrum Karlsruhe Institut fuer Angewandte Informatik
pp. 533
Session 10C: New Technologies for Mixed-Signal Test

Exploit Analog IFA to Improve Specification Based Tests (Abstract)

Bert Atzema , Philips Research Laboratories Eindhoven, The Netherlands
Taco Zwemstra , Philips Research Laboratories Eindhoven, The Netherlands
pp. 542

Analogue Fault Modelling and Simulation for Supply Current Monitoring (Abstract)

B.R. Wilkins , University of Southampton
M. Zwolinski , University of Southampton
C. Chalk , University of Southampton
pp. 547
Session 11A: Recent Advances in Simulation

Fast Computation of Substrate Resistances in Large Circuits (Abstract)

T. Smedes , Delft University of Technology
A.J. Van Genderen , Delft University of Technology
N.P. van der Meijs , Delft University of Technology
pp. 560

ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits (Abstract)

Elyse Rosenbaum , University of Illinois at Urban-Champaign
Sung-Mo Kang , University of Illinois at Urban-Champaign
Yi-Kan Cheng , University of Illinois at Urban-Champaign
pp. 566

Simulated Annealing Algorithm with Multi-Molecule: An Approach to Analog Synthesis (Abstract)

H. Wang , Dept. of Electronic Engineering Tsinghua Univ., Beijing, P.R. China, 100084
R.S. Liu , Dept. of Electronic Engineering Tsinghua Univ., Beijing, P.R. China, 100084
C.Z. Fan , Dept. of Electronic Engineering Tsinghua Univ., Beijing, P.R. China, 100084
H.Z. Yang , Dept. of Electronic Engineering Tsinghua Univ., Beijing, P.R. China, 100084
pp. 571
Session 11C: DFT Solutions and IDDQ

Iddq Testing for High Performance CMOS - The Next Ten Years (Abstract)

R.H. Dennard , IBM, Yorktown, NY, USA
W. Maly , CMU, Pittsburgh, PA, USA
R. Kapur , IBM, Endicott, NY, USA
T.W. Williams , IBM, Boulder, CO, USA
M.R. Mercer , Texas A&M, College Station, TX, USA
pp. 578

Design for Testability of Gated-Clock FSMs (Abstract)

M. Favalli , DEIS - University of Bologna
L. Benini , CIS - Stanford University
G. de Micheli , CIS - Stanford University
pp. 589
Poster Session

VLSI Design of a High Speed Soft Decision Viterbi Detector (PDF)

Tom Conway , University of Limerick
John Nelson , University of Limerick
pp. 598

A Hardware/Software Codesign Case Study: Design of a Robot Arm Controller (PDF)

Mohamed Abid , TIMA Laboratory, 46 avenue Felix Viallet 38031 Grenoble Cedex, FRANCE
Adel Changuel , TIMA Laboratory, 46 avenue Felix Viallet 38031 Grenoble Cedex, FRANCE
Ahmed Jerraya , TIMA Laboratory, 46 avenue Felix Viallet 38031 Grenoble Cedex, FRANCE
pp. 599

A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis (PDF)

Peter Marwedel , University of Dortmund, Informatik XII Otto-Hahn-Str. 16, 44221 Dortmund, Germany
Rainer Dömer , University of Dortmund, Informatik XII Otto-Hahn-Str. 16, 44221 Dortmund, Germany
Steven Bashford , University of Dortmund, Informatik XII Otto-Hahn-Str. 16, 44221 Dortmund, Germany
Birger Landwehr , University of Dortmund, Informatik XII Otto-Hahn-Str. 16, 44221 Dortmund, Germany
Ingolf Markhof , University of Dortmund, Informatik XII Otto-Hahn-Str. 16, 44221 Dortmund, Germany
pp. 600

Algebraic Support for Transformational Hardware Allocation (PDF)

J.M. Mendias , Universidad Complutense de Madrid
M. Fernandez , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
pp. 601

A spectral method for Boolean function matching (PDF)

D.M. Miller , Dept. of Comput. Sci., Victoria Univ., BC, Canada
pp. 602

FPGA synthesis for minimum area, delay and power (PDF)

K.-R.R. Pan , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 603

An Efficient Method for the Self-Consistent Electro-Thermal Simulation and its Integration into a CAD Framework (PDF)

Vladimir Szekely , Technical University of Budapest
Alpar Csendes , Technical University of Budapest
Gabor Farkas , Technical University of Budapest
Andras Pahi , Technical University of Budapest
Marta Rencz , Technical University of Budapest
Andras Poppe , Technical University of Budapest
pp. 604

A System for Modelling and Proving Circuits (PDF)

Michel Allemand , Laboratoire d'Informatique de Marseille -- URA CNRS 1787
Jean-Luc Paillet , Laboratoire d'Informatique de Marseille -- URA CNRS 1787
Solange Coupet-Grimal , Laboratoire d'Informatique de Marseille -- URA CNRS 1787
Line Jakubiec , Laboratoire d'Informatique de Marseille -- URA CNRS 1787
pp. 605

Exploiting Partitioned Transition Relations for Efficient Symbolic Model Checking in CTL (PDF)

Ales Casar , University of Maribor
Zmago Brezocnik , University of Maribor
Tatjana Kapus , University of Maribor
pp. 606

Generalized Recognition of Gates: A VLSI Abstraction Tool (PDF)

Jean Bruce Guignet , BULL Electronic Engineering Services
pp. 608

A Combined Pairing and Chaining Algorithm for CMOS Layout Generation (PDF)

Xavier Marin , Centre Nacional de Microelectronica, IMB-CNM(CSIC)
A. Josep Velasco , Centre Nacional de Microelectronica, IMB-CNM(CSIC)
Rafael Peset Llopis , Philips Research Laboratories
Jordi Carrabina , Centre Nacional de Microelectronica, IMB-CNM(CSIC)
pp. 609

Hardware Check of Arithmetic Devices with Abridged Execution of Operations (PDF)

Alexander Drozd , Odessa State Politechnic University
Wael Hassonah , Odessa State Politechnic University
Michel Lobachov , Odessa State Politechnic University
pp. 611

Realistic Fault Extraction for Boards (PDF)

P.Y.K. Cheung , Department of Electrical and Electronic Engineering Imperial College, London SW7 2BT, U.K
J.T. Sousa , Department of Electrical and Electronic Engineering Imperial College, London SW7 2BT, U.K
T. Shen , Department of Electrical and Electronic Engineering Imperial College, London SW7 2BT, U.K
pp. 612

System Fault Diagnosis based on a Fuzzy Qualitative Approach (PDF)

M.H. Touati , TIMA Laboratory, 46 avenue Felix Viallet 38031 Grenoble Cedex, FRANCE
M. Marzouki , TIMA Laboratory, 46 avenue Felix Viallet 38031 Grenoble Cedex, FRANCE
F. Mohamed , TIMA Laboratory, 46 avenue Felix Viallet 38031 Grenoble Cedex, FRANCE
pp. 616

Methods and Tools for the Design of Electrostatic Micromotors (PDF)

K. Hameyer , Katholieke Universiteit Leuven
R. Belmans , Katholieke Universiteit Leuven
Tb. Johansson , Katholieke Universiteit Leuven
pp. 618

Author Index (PDF)

pp. 621
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