European Design and Test Conference (1996)
Mar. 11, 1996 to Mar. 14, 1996
Michael S. Hsiao , Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL 61801
Elizabeth M. Rudnick , Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL 61801
Janak H. Patel , Center for Reliable and High-Performance Computing University of Illinois, Urbana, IL 61801
This research was supported in part by the Semiconductor Research Corporation under contract SRC 95-DP-109, in part by ARPA under contract DABT63-95-C-0069, and by Hewlett-Packard under an equipment grant. A new sequential circuit test generator, ALT-TEST, is described which alternates repeatedly between two phases of test generation. The first phase uses a simulation-based genetic algorithm, while the second phase uses a deterministic algorithm. The fast execution of the first phase combines with the more powerful test sequence generation and redundancy-identification capabilities of the second phase to produce test sets having high fault coverages in low execution times. The effectiveness of the approach is demonstrated on the ISCAS89 sequential benchmark circuits and several synthesized circuits.
Genetic algorithms, hybrid, automatic test generation
J. H. Patel, M. S. Hsiao and E. M. Rudnick, "Alternating Strategies for Sequential Circuit ATPG," European Design and Test Conference(EDTC), Paris, FRANCE, 1996, pp. 368.