The Community for Technology Leaders
European Design and Test Conference (1996)
Paris, FRANCE
Mar. 11, 1996 to Mar. 14, 1996
ISSN: 1066-1409
ISBN: 0-8186-7423-7
pp: 102
Johan van Praet , IMEC (VSDM) Kapeldreef 75, B-3001 Leuven, Belgium
Dirk Lanneer , IMEC (VSDM) Kapeldreef 75, B-3001 Leuven, Belgium
Gert Goossens , IMEC (VSDM) Kapeldreef 75, B-3001 Leuven, Belgium
Werner Geurts , IMEC (VSDM) Kapeldreef 75, B-3001 Leuven, Belgium
Hugo de Man , IMEC (VSDM) Kapeldreef 75, B-3001 Leuven, Belgium
ABSTRACT
Embedded processors in electronic systems typically are tuned to a few applications. Development of processor specific compilers is prohibitively expensive and as a result such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a retargetable and optimising code generator. It uses a graph based processor model that captures the connectivity, the parallelism and all architectural peculiarities of an embedded processor. In this paper, the processor model is presented and we formally define the code generation task, including code selection, register allocation and scheduling, in terms of this model.
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CITATION

G. Goossens, H. de Man, W. Geurts, D. Lanneer and J. van Praet, "A Graph Based Processor Model for Retargetable Code Generation," European Design and Test Conference(EDTC), Paris, FRANCE, 1996, pp. 102.
doi:10.1109/EDTC.1996.494133
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