The Community for Technology Leaders
European Design and Test Conference (1995)
Paris, France
Mar. 6, 1995 to Mar. 9, 1995
ISSN: 1066-1409
ISBN: 0-8186-7039-8
TABLE OF CONTENTS
Session 1A: DSP and Multimedia

A prototype VLSI chip architecture for JPEG image compression (Abstract)

M. Kovac , Fac. of Electr. Eng., Zagreb Univ., Croatia
N. Ranganathan , Fac. of Electr. Eng., Zagreb Univ., Croatia
M. Zagar , Fac. of Electr. Eng., Zagreb Univ., Croatia
pp. 2

A variant of Cooley-Tuckey algorithm with local memory management (Abstract)

S.J. Wei , Lab. of Microelectron., Faculte Polytech. de Mons, Belgium
R.G. Crappe , Lab. of Microelectron., Faculte Polytech. de Mons, Belgium
J. Leroy , Lab. of Microelectron., Faculte Polytech. de Mons, Belgium
J.-M. Bourguet , Lab. of Microelectron., Faculte Polytech. de Mons, Belgium
T. Nancy , Lab. of Microelectron., Faculte Polytech. de Mons, Belgium
pp. 7

Eliminating the Z-Buffer bottleneck (Abstract)

A. Schilling , WSI/GRIS, Tubingen Univ., Germany
G. Knittel , WSI/GRIS, Tubingen Univ., Germany
pp. 12
Session 1B: Mixed-Signal DFT

Mixed-Signal DFT (PDF)

pp. null

Defect-oriented test methodology for complex mixed-signal circuits (Abstract)

F.C.M. Kuijstermans , Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
M. Sachdev , Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
A.P. Thijssen , Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 18

A design-for-test structure for optimising analogue and mixed signal IC test (Abstract)

A.M.D. Richardson , Dept. of Eng., Lancaster Univ., UK
A.P. Dorey , Dept. of Eng., Lancaster Univ., UK
A.H. Bratt , Dept. of Eng., Lancaster Univ., UK
R.J.A. Harvey , Dept. of Eng., Lancaster Univ., UK
pp. 24

Mixed-signal circuits and boards for high safety applications (Abstract)

C. Nielsen , DELET, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
B. Courtois , DELET, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
S. Mir , DELET, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
V. Kolarik , DELET, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
M. Lubaszewski , DELET, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
pp. 34
Session 1C: Exact Methods in Architectural Timing Optimization

Exact scheduling strategies based on bipartite graph matching (Abstract)

J.A.G. Jess , Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
A.H. Timmer , Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
pp. 42

On applicability of symbolic techniques to larger scheduling problems (Abstract)

F. Brewer , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
I. Radivojevic , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 48

Optimizing synchronous systems for multi-dimensional applications (Abstract)

Liang-Fang Chao , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
N.L. Passos , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
E.H.-M. Sha , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 54
Session 2A: Circuit Partitioning

When clusters meet partitions: new density-based methods for circuit decomposition (Abstract)

D.J.-H. Huang , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
A.B. Kahng , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 60

Circuit clustering for delay minimization under area and pin constraints (Abstract)

Honghua Yang , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 65

Architecture driven k-way partitioning for multichip modules (Abstract)

A.A. Schoene , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
B.M. Riess , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
pp. 71
Panel Session 2B
Session 2C: Combinational Logic Synthesis

Synthesis of multilevel fault-tolerant combinational circuits (Abstract)

A. Bogliolo , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
M. Damiani , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
pp. 80

Improved technology mapping using a new approach to Boolean matching (Abstract)

B. Kapoor , Integrated Syst. Lab., Texas Instrum. Inc., Dallas, TX, USA
pp. 86

Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions (Abstract)

B. Becker , Dept. of Comput. Sci., Frankfurt Univ., Germany
R. Drechsler , Dept. of Comput. Sci., Frankfurt Univ., Germany
pp. 91
Session 3A: Designs and Tools for Analogue and Mixed Signal ICs

Low-voltage low-power switched-current circuits and systems (Abstract)

Nianxiong Tan , Dept. of Electr. Eng., Linkoping Univ., Sweden
S. Eriksson , Dept. of Electr. Eng., Linkoping Univ., Sweden
pp. 100

Low supply voltage, low noise fully differential programmable gain amplifiers (Abstract)

D. Strle , Microelectron. Lab., Ljubljana Univ., Slovenia
J. Trontelj , Microelectron. Lab., Ljubljana Univ., Slovenia
A. Pletersek , Microelectron. Lab., Ljubljana Univ., Slovenia
pp. 105

A universal telephone audio circuit with loudhearing and handsfree operation in CMOS technology (Abstract)

K. Hayat-Dawoodi , Austria Mikro Syst. Int. AG, Unterpremstatten, Austria
O. Alminde , Austria Mikro Syst. Int. AG, Unterpremstatten, Austria
V. Kunc , Austria Mikro Syst. Int. AG, Unterpremstatten, Austria
M. Pauritsch , Austria Mikro Syst. Int. AG, Unterpremstatten, Austria
pp. 113

A flexible topology selection program as part of an analog synthesis system (Abstract)

G. Gielen , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
P. Veselinovic , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
D. Leenaerts , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
F. Proesmans , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
F. Leyn , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
W. Sansen , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
W. van Bokhoven , Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
pp. 119
Session 3B: Memory Testing

Memory Testing (PDF)

pp. null

Pseudo-exhaustive word-oriented DRAM testing (Abstract)

V.N. Yarmolik , Boston Univ., MA, USA
M.G. Karpovsky , Boston Univ., MA, USA
A.J. van de Goor , Boston Univ., MA, USA
pp. 126

Functional test for shifting-type FIFOs (Abstract)

A.J. van de Goor , Delft Univ. of Technol., Netherlands
I. Schanstra , Delft Univ. of Technol., Netherlands
Y. Zorian , Delft Univ. of Technol., Netherlands
pp. 133

A 370-MHz memory built-in self-test state machine (Abstract)

G.S. Koch , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
L. Ternullo, Jr. , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
R.D. Adams , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
J. Connor , Microelectron. Div., IBM Corp., Essex Junction, VT, USA
pp. 139
Session 3C: Sequential Logic Synthesis

Modeling and optimization of hierarchical synchronous circuits (Abstract)

T. Kolks , IMEC, Leuven, Belgium
G. de Jong , IMEC, Leuven, Belgium
B. Lin , IMEC, Leuven, Belgium
pp. 144

Improving initialization through reversed retiming (Abstract)

I. Spillinger , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
G. Even , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
L. Stok , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 150

Elimination of multi-cycle false paths by state encoding (Abstract)

Z. Hasan , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
M.J. Ciesielski , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 155
Session 4A: High Speed Telecom Design

Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC (Abstract)

J.C. Diaz , Telefonica Investigacion y Desarrollo, Madrid, Spain
P. Scarfone , Telefonica Investigacion y Desarrollo, Madrid, Spain
L. Merayo , Telefonica Investigacion y Desarrollo, Madrid, Spain
M. Zamboni , Telefonica Investigacion y Desarrollo, Madrid, Spain
M. Barbini , Telefonica Investigacion y Desarrollo, Madrid, Spain
P. Plaza , Telefonica Investigacion y Desarrollo, Madrid, Spain
F. Calvo , Telefonica Investigacion y Desarrollo, Madrid, Spain
pp. 162

Post-layout optimization of power and timing for ECL LSIs (Abstract)

H. Kitazawa , NTT LSI Labs., Atsugi, Japan
A. Onozawa , NTT LSI Labs., Atsugi, Japan
K. Kawai , NTT LSI Labs., Atsugi, Japan
pp. 167

A 622/155 mbps ATM line terminator mono-chip (Abstract)

D. Belot , SGS-Thomson, Crolles, France
P. Delerue , SGS-Thomson, Crolles, France
M. Diaz Nava , SGS-Thomson, Crolles, France
J. Bulone , SGS-Thomson, Crolles, France
pp. 173
Session 4B: System Synthesis

System Synthesis (PDF)

pp. null

A unified model for co-simulation and co-synthesis of mixed hardware/software systems (Abstract)

M. Abid , Syst. Level Synthesis Group, Inst. Nat. Polytech. de Grenoble, France
A.A. Jerraya , Syst. Level Synthesis Group, Inst. Nat. Polytech. de Grenoble, France
C.A. Valderrama , Syst. Level Synthesis Group, Inst. Nat. Polytech. de Grenoble, France
A. Changuel , Syst. Level Synthesis Group, Inst. Nat. Polytech. de Grenoble, France
P.V. Raghavan , Syst. Level Synthesis Group, Inst. Nat. Polytech. de Grenoble, France
T. Ben Ismail , Syst. Level Synthesis Group, Inst. Nat. Polytech. de Grenoble, France
pp. 180

SLIF: a specification-level intermediate format for system design (Abstract)

F. Vahid , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
D.D. Gajski , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
pp. 185
Session 4C: Advanced DFT Techniques

High-level synthesis for easy testability (Abstract)

M.L. Flottes , Lab. d'Inf., de Robotique et de Microelectron., CNRS, Montpellier, France
B. Rouzeyre , Lab. d'Inf., de Robotique et de Microelectron., CNRS, Montpellier, France
D. Hammad , Lab. d'Inf., de Robotique et de Microelectron., CNRS, Montpellier, France
pp. 198

Sequential logic minimization based on functional testability (Abstract)

F. Fummi , Dipartimento di Elettronica, Politecnico di Milano, Italy
D. Sciuto , Dipartimento di Elettronica, Politecnico di Milano, Italy
M. Serra , Dipartimento di Elettronica, Politecnico di Milano, Italy
pp. 207

A Gauss-elimination based PRPG for combinational circuits (Abstract)

Li-Ren Huang , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Ing-Yi Chen , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Sy-Yen Kuo , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 212
Session 5A: Digital and System Simulation

Mixed-signal modelling in VHDL for system-on-chip applications (Abstract)

S. Blanc , RGS Div., Thomson-CSF, Gennesvilliers, France
B. Candaele , RGS Div., Thomson-CSF, Gennesvilliers, France
F. Pichon , RGS Div., Thomson-CSF, Gennesvilliers, France
pp. 218

Run-time consistency checking in discrete simulation models (Abstract)

J.A.G. Jess , Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
C.A.J. van Eijk , Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
J.W.G. Fleurkens , Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
pp. 223

Delay models for the sea-of-wires array synthesis system (Abstract)

Ing-Yi Chen , Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
Sy-Yen Kuo , Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
Geng-Lin Chen , Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
pp. 228
Session 5B: Code Generation

Code Generation (PDF)

pp. null

A unified scheduling model for high-level synthesis and code generation (Abstract)

A. Kifli , IMEC, Leuven, Belgium
H. De Man , IMEC, Leuven, Belgium
G. Goosens , IMEC, Leuven, Belgium
pp. 234

A BDD-based frontend for retargetable compilers (Abstract)

P. Marwedel , Dept. of Comput. Sci., Dortmund Univ., Germany
R. Leupers , Dept. of Comput. Sci., Dortmund Univ., Germany
pp. 239

Efficient code generation for in-house DSP-cores (Abstract)

M. Strik , Philips Res. Lab., Eindhoven, Netherlands
S. Note , Philips Res. Lab., Eindhoven, Netherlands
J. Jess , Philips Res. Lab., Eindhoven, Netherlands
J. van Meerbergen , Philips Res. Lab., Eindhoven, Netherlands
A. Timmer , Philips Res. Lab., Eindhoven, Netherlands
pp. 244
Session 5C: Sequential ATPG and Diagnosis

Complexity of sequential ATPG (Abstract)

W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
T.E. Marchok , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J. Rajski , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
A. El-Maleh , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 252

Improved sequential ATPG using functional observation information and new justification methods (Abstract)

Chanhee Oh , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Jaehong Park , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M.R. Mercer , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 262

GARDA: a diagnostic ATPG for large synchronous sequential circuits (Abstract)

F. Corno , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Rebaudengo , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 267
Session 6A: CAD Frameworks

CAD Frameworks (PDF)

pp. null

Controlling change propagation and project policies in IC design (Abstract)

S. Soudagar , Semicond. Syst. Design Technol., Motorola Inc., USA
Y. Mathys , Semicond. Syst. Design Technol., Motorola Inc., USA
M. Morgan , Semicond. Syst. Design Technol., Motorola Inc., USA
pp. 274

Generic design flows for project management in a framework environment (Abstract)

A. Kunzmann , Comput. Sci. Res. Center, Forschungszentrum Inf., Karlsruhe, Germany
E. Kwee-Christoph , Comput. Sci. Res. Center, Forschungszentrum Inf., Karlsruhe, Germany
F. Feldbusch , Comput. Sci. Res. Center, Forschungszentrum Inf., Karlsruhe, Germany
R. Kumar , Comput. Sci. Res. Center, Forschungszentrum Inf., Karlsruhe, Germany
pp. 280

Enhanced functionality by coupling the JESSI-COMMON-Framework with an ECAD framework (Abstract)

R. Seepold , Forschungszentrum Inf., Karlsruhe, Germany
A. Kunzmann , Forschungszentrum Inf., Karlsruhe, Germany
pp. 285
Panel Session 6B
Session 6C: Test Generation and Testability

Enhanced testing performance via unbiased test sets (Abstract)

M.R. Mercer , Texas Univ., Austin, TX, USA
L.-C. Wang , Texas Univ., Austin, TX, USA
T.W. Williams , Texas Univ., Austin, TX, USA
pp. 294

A testability measure for hierarchical design environments (Abstract)

D.L. Tao , Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
M.H.C. Lee , Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
pp. 303

Gate delay fault test generation for non-scan circuits (Abstract)

H.G. Kerkhoff , MESA Res. Inst., Twente Univ., Enschede, Netherlands
H.T. Vierhaus , MESA Res. Inst., Twente Univ., Enschede, Netherlands
G. Van Brakel , MESA Res. Inst., Twente Univ., Enschede, Netherlands
U. Glaser , MESA Res. Inst., Twente Univ., Enschede, Netherlands
pp. 308
Session 7A: Applications of Symbolic Traversal Techniques

Verifying real-time properties of MOS-transistor circuits (Abstract)

J. Frossl , Inst. fur Rechnerentwurf und Fehlertoleranz, Karlsruhe Univ., Germany
T. Kropf , Inst. fur Rechnerentwurf und Fehlertoleranz, Karlsruhe Univ., Germany
pp. 314

Using symbolic techniques to find the maximum clique in very large sparse graphs (Abstract)

F. Corno , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 320

Checking signal transition graph implementability by symbolic BDD traversal (Abstract)

J. Cortadella , Aizu Univ., Aizu-Wakamatsu, Japan
M. Kishinevsky , Aizu Univ., Aizu-Wakamatsu, Japan
E. Pastor , Aizu Univ., Aizu-Wakamatsu, Japan
A. Yakovlev , Aizu Univ., Aizu-Wakamatsu, Japan
O. Roig , Aizu Univ., Aizu-Wakamatsu, Japan
A. Kondratyev , Aizu Univ., Aizu-Wakamatsu, Japan
pp. 325

Proving testing preorders for process algebra descriptions (Abstract)

P. Prinetto , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
F. Corno , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Cusinato , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Ferrero , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 333
Session 7B: Handling Physical Constraints in Architectural Synthesis

Architectural exploration for datapaths with memory hierarchy (Abstract)

D.D. Gajski , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
N.D. Holmes , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 340

Design reuse through high-level library mapping (Abstract)

P.K. Jha , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
N.D. Dutt , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 345

Automatic clock tree generation in ASIC designs (Abstract)

A. Balboni , Res. & Dev. Lab., Italtel Telecom Co, Italy
A. Pellencin , Res. & Dev. Lab., Italtel Telecom Co, Italy
M. Quadrini , Res. & Dev. Lab., Italtel Telecom Co, Italy
D. Sciuto , Res. & Dev. Lab., Italtel Telecom Co, Italy
C. Costi , Res. & Dev. Lab., Italtel Telecom Co, Italy
pp. 351
Session 7C: Self-Checking Approaches

Area versus detection latency trade-offs in self-checking memory design (Abstract)

M. Nicolaidis , Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
Y. Zorian , Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
O. Kebichi , Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
pp. 358

Self-checking architectures for fast Hartley transform (Abstract)

S.S. Dlay , Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK
O.R. Hinton , Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK
J.M. Tahir , Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK
R.N.G. Naguib , Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK
pp. 363

Built-in intermediate voltage testing for CMOS circuits (Abstract)

Kuen-Jong Lee , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Jing-Jou Tang , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Bin-Da Liu , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 372
Session 8A: Design Methodologies

Design and test of the PowerPC 603 microprocessor (Abstract)

R. Reed , IBM Corp., Austin, TX, USA
C.H. Malley , IBM Corp., Austin, TX, USA
Sung Park , IBM Corp., Austin, TX, USA
E.K. Vida-Torku , IBM Corp., Austin, TX, USA
pp. 378

An ASIC design for real-time image processing in industrial applications (Abstract)

G. Nateri , Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
G.M. Bisio , Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
D.D. Caviglia , Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
M. Valle , Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
L. Briozzo , Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
pp. 385

Rapid prototype of a hardware emulator for a SIMD processor array (Abstract)

A. Wheeler , Dept. of Electr. Eng., Arkansas Univ., USA
C. Kancler , Dept. of Electr. Eng., Arkansas Univ., USA
B. Wealand , Dept. of Electr. Eng., Arkansas Univ., USA
D.L. Andrews , Dept. of Electr. Eng., Arkansas Univ., USA
pp. 391
Session 8B: Power and Delay Issues in Logic Synthesis

Analysis and reduction of glitches in synchronous networks (Abstract)

J. van Meerbergen , Philips Res. Lab., Eindhoven, Netherlands
J. Jess , Philips Res. Lab., Eindhoven, Netherlands
J. Leijten , Philips Res. Lab., Eindhoven, Netherlands
pp. 398

Decomposition of logic functions for minimum transition activity (Abstract)

A. Sangiovanni-Vincentelli , Fujitsu Labs. of America Inc., San Jose, CA, USA
R.K. Brayton , Fujitsu Labs. of America Inc., San Jose, CA, USA
R. Murgai , Fujitsu Labs. of America Inc., San Jose, CA, USA
pp. 404

Prediction of interconnect delay in logic synthesis (Abstract)

S. Malik , EPIC Desing Technol. Inc., Santa Clara, CA, USA
H.H.-F. Jyu , EPIC Desing Technol. Inc., Santa Clara, CA, USA
pp. 411
Session 8C: BIST Methodologies

A BIST approach to delay fault testing with reduced test length (Abstract)

K. Fuchs , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
B. Wurth , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
pp. 418

BIST hardware generator for mixed test scheme (Abstract)

C. Dufaza , Lab. d'Inf., de Robotique et de Micro-Electron., CNRS, Montpellier, France
C. Chevalier , Lab. d'Inf., de Robotique et de Micro-Electron., CNRS, Montpellier, France
H. Viallon , Lab. d'Inf., de Robotique et de Micro-Electron., CNRS, Montpellier, France
pp. 424

Accumulator-based BIST approach for stuck-open and delay fault testing (Abstract)

C. Halatsis , Inst. of Inf. & Telecommun., NCSR Demokritos, Athens, Greece
A. Paschalis , Inst. of Inf. & Telecommun., NCSR Demokritos, Athens, Greece
I. Voyiatzis , Inst. of Inf. & Telecommun., NCSR Demokritos, Athens, Greece
D. Nikolos , Inst. of Inf. & Telecommun., NCSR Demokritos, Athens, Greece
pp. 431
Session 9A: New Developments in Logic Representation and Verification Techniques

How many decomposition types do we need? [decision diagrams] (Abstract)

R. Drechsler , Dept. of Comput. Sci., Frankfurt Univ., Germany
B. Becker , Dept. of Comput. Sci., Frankfurt Univ., Germany
pp. 438

VERIFUL: VERIfication using FUnctional Learning (Abstract)

M. Fujita , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
J. Jain , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
R. Mukherjee , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 444

Implicit manipulation of polynomials using zero-suppressed BDDs (Abstract)

S. Minato , NTT LSI Labs., Kanagawa, Japan
pp. 449
Session 9C: Test Preparation for Mixed-Signal Systems

Automatic test vector generation for mixed-signal circuits (Abstract)

B. Ayari , Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Ecole Polytech. de Montreal, Que., Canada
N. Ben Hamida , Ecole Polytech. de Montreal, Que., Canada
pp. 458

Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits (Abstract)

C. Sebeke , Lab. fur Informationstechnol., Hannover Univ., Germany
M.J. Ohletz , Lab. fur Informationstechnol., Hannover Univ., Germany
J.P. Teixeira , Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 464

Achieving simulation-based test program verification and fault simulation capabilities for mixed-signal systems (Abstract)

C. Abraham , Siemens Automotive, Toulouse, France
P. Caunegre , Siemens Automotive, Toulouse, France
pp. 469
Session 10A: Hierarchical Layout

The effect of pin constraints on layout area (Abstract)

J. Altmeyer , Kaiserslautern Univ., Germany
B. Schurmann , Kaiserslautern Univ., Germany
pp. 480

EMC-driven midway routing on PCBs (Abstract)

D. Theune , Cadlab/ASE, Paderborn Univ./Siemens Nixdorf Informationssyst. AG Joint R&D Inst., Germany
T. Lengauer , Cadlab/ASE, Paderborn Univ./Siemens Nixdorf Informationssyst. AG Joint R&D Inst., Germany
R. Thiele , Cadlab/ASE, Paderborn Univ./Siemens Nixdorf Informationssyst. AG Joint R&D Inst., Germany
H. Schmidt , Cadlab/ASE, Paderborn Univ./Siemens Nixdorf Informationssyst. AG Joint R&D Inst., Germany
pp. 486

A hybrid hierarchical approach for multi-layer global routing (Abstract)

M. Hayashi , Fac. of Sci. & Eng., Chuo Univ., Tokyo, Japan
S. Tsukiyama , Fac. of Sci. & Eng., Chuo Univ., Tokyo, Japan
pp. 492
Session 10B: Modeling and Design of ASIPs

Software estimation using a generic-processor model (Abstract)

S. Narayan , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Jie Gong , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
D.D. Gajski , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 498

Describing instruction set processors using nML (Abstract)

A. Fauth , Inst. fur Tech. Inf., Tech. Univ. Berlin, Germany
J. Van Praet , Inst. fur Tech. Inf., Tech. Univ. Berlin, Germany
M. Freericks , Inst. fur Tech. Inf., Tech. Univ. Berlin, Germany
pp. 503

Incorporating compiler feedback into the design of ASIPs (Abstract)

N. Dutt , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
F. Onion , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
A. Nicolau , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 508
Session 10C: Delay Testing and Diagnosis

An efficient method for computing exact path delay fault coverage (Abstract)

B. Kapoor , Integrated Syst. Labs., Texas Instrum. Inc., Dallas, TX, USA
pp. 516

Bit parallel test pattern generation for path delay faults (Abstract)

H. Wittman , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
M. Henftling , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
pp. 521

A trace-based method for delay fault diagnosis in synchronous sequential circuits (Abstract)

B. Rodriguez , Lab. d'Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
P. Girard , Lab. d'Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
S. Pravossoudovitch , Lab. d'Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
C. Landrault , Lab. d'Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 526
Session 11A: New Applications of Analogue Simulation Algorithms

Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures (Abstract)

M. Kamon , Res. Lab. of Electron., MIT, Cambridge, MA, USA
L.M. Silveira , Res. Lab. of Electron., MIT, Cambridge, MA, USA
J. White , Res. Lab. of Electron., MIT, Cambridge, MA, USA
pp. 534

On software development to support statistical simulation of analogue circuits (Abstract)

O. Jarov , Dept. of Microelectron., Byelorussian State Univ. of Inf. & Radioelectron., Minsk, Byelorussia
A. Sukhodolsky , Dept. of Microelectron., Byelorussian State Univ. of Inf. & Radioelectron., Minsk, Byelorussia
E. Driouk , Dept. of Microelectron., Byelorussian State Univ. of Inf. & Radioelectron., Minsk, Byelorussia
pp. 539

Multilevel thermal simulation of MCM's by system 'MONSTR-M' (Abstract)

V.A. Koval , State Univ., Lviv, Ukraine
D.V. Fedasyuk , State Univ., Lviv, Ukraine
pp. 544
Session 11B: Design Problems in Pipelines

Combining MBP-speculative computation and loop pipelining in high-level synthesis (Abstract)

R. Ernst , Tech. Univ. Braunschweig, Germany
U. Holtmann , Tech. Univ. Braunschweig, Germany
pp. 550

PPS: a pipeline path-based scheduler (Abstract)

M. Rahmouni , Lab. TIMA, Inst. Nat. Polytech. de Grenoble, France
A.A. Jerraya , Lab. TIMA, Inst. Nat. Polytech. de Grenoble, France
pp. 557

Balancing structural hazards and hardware cost of pipelined processors (Abstract)

A.E. Casavant , C&C Res. Lab., NEC USA Inc., Princeton, NJ, USA
pp. 562
Session 11C: IDDQ Testing

IDDQ Testing (PDF)

pp. null

Correlation between I/sub DDQ/ testing quality and sensor accuracy (Abstract)

M. Dalpasso , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
M. Favalli , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
P. Olivo , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
pp. 568

Synthesis of I/sub DDQ/-testable circuits: integrating built-in current sensors (Abstract)

J. Figueras , Inst. of Comput. Structures, Siegen Univ., Germany
H.-J. Wunderlich , Inst. of Comput. Structures, Siegen Univ., Germany
M. Herzog , Inst. of Comput. Structures, Siegen Univ., Germany
A. Calderon , Inst. of Comput. Structures, Siegen Univ., Germany
J.A. Carrasco , Inst. of Comput. Structures, Siegen Univ., Germany
pp. 573

A built-in quiescent current monitor for CMOS VLSI circuits (Abstract)

E. Janssens , Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
A. Rubio , Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
D. Mateo , Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
H. Casier , Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
J. Segura , Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
P. De Pauw , Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
J. Figueras , Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 581
Poster Session

High speed communications links for ASICs (PDF)

I. Montandon , LSI Logic Corp., CA, USA
D. Burrows , LSI Logic Corp., CA, USA
K. Hunt , LSI Logic Corp., CA, USA
pp. 588

TRJM: a high speed programmable ATM-SDH mapper (PDF)

J.L. Conesa , Telefonica Investigacion y Desarrollo, Madrid, Spain
R. Caravantes , Telefonica Investigacion y Desarrollo, Madrid, Spain
F. Calvo , Telefonica Investigacion y Desarrollo, Madrid, Spain
J.I. Solana , Telefonica Investigacion y Desarrollo, Madrid, Spain
J. Crespo , Telefonica Investigacion y Desarrollo, Madrid, Spain
pp. 589

Artificial neural networks in medical decision making systems: an application to pulmonary diseases' diagnosis through VHDL synthesis (PDF)

G.-P.K. Economou , VLSI Design Lab., Patras Univ., Greece
C.E. Goutis , VLSI Design Lab., Patras Univ., Greece
J.A. Hallas , VLSI Design Lab., Patras Univ., Greece
E.P. Mariatos , VLSI Design Lab., Patras Univ., Greece
pp. 590

Integration of an expert system for analogue layout synthesis into a commercial CAD framework (PDF)

R.J. Mack , Centre for VLSI Design, Essex Univ., Colchester, UK
D.A. Bensouiah , Centre for VLSI Design, Essex Univ., Colchester, UK
R.E. Massara , Centre for VLSI Design, Essex Univ., Colchester, UK
pp. 591

Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams (PDF)

R. Drechsler , Dept. of Comput. Sci., Frankfurt Univ., Germany
B. Becker , Dept. of Comput. Sci., Frankfurt Univ., Germany
pp. 592

Efficient synthesis of fault-tolerant controllers (PDF)

R. Rochet , Inst. Nat. Polytech. de Grenoble, France
G. Saucier , Inst. Nat. Polytech. de Grenoble, France
R. Leveugle , Inst. Nat. Polytech. de Grenoble, France
pp. 593

A balanced multilevel decomposition method (PDF)

T. Luba , Inst. of Telecommun., Warsaw Univ. of Technol., Poland
H. Selvaraj , Inst. of Telecommun., Warsaw Univ. of Technol., Poland
pp. 594

A precise event-driven circuit simulator based on predicted fan-in voltages (PDF)

T. Kitaura , Fujitsu Labs. Ltd., Atsugi, Japan
F. Kawafuji , Fujitsu Labs. Ltd., Atsugi, Japan
T. Kage , Fujitsu Labs. Ltd., Atsugi, Japan
H. Fujisawa , Fujitsu Labs. Ltd., Atsugi, Japan
pp. 595

Network initialization in a switch-level simulator (PDF)

A.J. Van Genderen , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 596

SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects (PDF)

W. Kuzmicz , Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Poland
W. Pleskacz , Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Poland
pp. 598

A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs (PDF)

M. Favalli , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
B. Ricco , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
L. Penza , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
pp. 599

A method for testability analysis and BIST insertion at the RTL (PDF)

J. Carletta , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
C. Papachristou , Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
pp. 600

Thermal test and monitoring [microelectronic structures] (PDF)

M. Rencz , Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
V. Szekely , Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
pp. 601

On testability of checkable digital circuits under pseudorandom signals (PDF)

V. Groll , Kiev Polytech. Inst., Ukraine
A. Romankevich , Kiev Polytech. Inst., Ukraine
pp. 602

Imperfect linear duplication of combinational circuits (PDF)

Y.L. Stolov , Kazan State Univ., Russia
R.Kh. Latypov , Kazan State Univ., Russia
pp. 603

Test preparation methodology for high coverage of physical defects in CMOS digital ICs (PDF)

I. Teixeira , INESC, Lisbon, Portugal
M.B. Santos , INESC, Lisbon, Portugal
J.P. Teixeira , INESC, Lisbon, Portugal
M. Simoes , INESC, Lisbon, Portugal
pp. 604

A comparative study of algorithms for A/D converter performance evaluation by statistical analysis (PDF)

G. Franco , Lab. de Microelectron., Bordeaux I Univ., Talence, France
D. Dallet , Lab. de Microelectron., Bordeaux I Univ., Talence, France
P. Marchegay , Lab. de Microelectron., Bordeaux I Univ., Talence, France
C. Morandi , Lab. de Microelectron., Bordeaux I Univ., Talence, France
pp. 606

A histogram method for analog-digital converters testing in time and spectral domain (PDF)

M. Sirovatkina , Inst. of Electron. & Comput. Sci., Acad. of Sci., Riga, Latvia
N. Semyonova , Inst. of Electron. & Comput. Sci., Acad. of Sci., Riga, Latvia
V. Zagursky , Inst. of Electron. & Comput. Sci., Acad. of Sci., Riga, Latvia
pp. 607

Index of Authors (PDF)

pp. 609
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