Reducing the Contention Experienced by Real-Time Core-to-I/O Flows over a Tilera-Like Network on Chip
2016 28th Euromicro Conference on Real-Time Systems (ECRTS) (2016)
July 5, 2016 to July 8, 2016
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ECRTS.2016.9
Many-core architectures are promising hardware to design real-time systems. However, the worst-case behavior of the Network-on-Chip (NoC) for both core-to-core and core-to-Input/Output (I/O) communications of critical applications must be established. The mapping over the NoC of both critical and non-critical applications has an impact on the network contention these critical communications exhibit. So far, all existing mapping strategies have focused on core-to-core communications. However, many-cores in embedded real-time systems will be integrated within backbone Ethernet networks, as they mostly provide Ethernet controllers as I/O interfaces. In a previous work we have shown that Ethernet packets can be dropped due to an internal congestion in a Tilera-like NoC. In this work, we describe and evaluate a mapping strategy for such Tilera-like NoCs that minimizes the contention of core-to-I/O critical flows in order to solve this problem. Experimental results on real avionics applications show significant improvements of core-to-IO flows transmission delays, without significantly impacting transmission delays of core-to-core flows.
embedded systems, local area networks, multiprocessing systems, network interfaces, network-on-chip, parallel architectures
L. Abdallah, M. Jan, J. Ermont and C. Fraboul, "Reducing the Contention Experienced by Real-Time Core-to-I/O Flows over a Tilera-Like Network on Chip," 2016 28th Euromicro Conference on Real-Time Systems (ECRTS), Toulouse, France, 2016, pp. 86-96.