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Engineering of Computer-Based Systems, IEEE International Conference on the (2004)
Brno, Czech Republic
May 24, 2004 to May 27, 2004
ISBN: 0-7695-2125-8
pp: 136
Kalpesh Zinjuwadia , The University of Kansas, Lawrence
Perry Alexander , The University of Kansas, Lawrence
ABSTRACT
Specification-based verification is increasingly being used when designing systems. In verification, the program under test is executed repeatedly and the obtained outputs and/or other parameters are compared against the expected values. This ensures that the implementation satisfies its specified functionality. In this paper, we present a tool, DVTG [Dvtg, design verification test generation from rosetta specifications], for automatically generating test vectors from Rosetta specifications. DVTG requires test requirements in XML format [http://www.w3schools.com/xml] and test scenarios, to generate these test vectors. For a given set of input parameters, the vectors represent desired output parameter values for the program under test . They can be further translated to specific inputs to run more concrete simulations. Later on, we discuss another tool, Test Harness, to authenticate a test program. We verify the output generated during test harnessing against the acceptance criteria generated from the specifications. We have proposed two major verifications to be performed during test harnessing, verifying the expected behavior and real-time requirements for the test program.
INDEX TERMS
Rosetta, DVTG, Test Scenarios, Test Vectors, Test Requirements, Test Initialization, XML, Test Harnessing
CITATION

P. Alexander and K. Zinjuwadia, "DVTG and Test Harnessing using Rosetta Specifications," Engineering of Computer-Based Systems, IEEE International Conference on the(ECBS), Brno, Czech Republic, 2004, pp. 136.
doi:10.1109/ECBS.2004.1316692
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