2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) (2016)
June 28, 2016 to July 1, 2016
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSN.2016.65
Instruction-Level Redundancy (ILR) is a well-known approach to tolerate transient CPU faults. It replicates instructions in a program and inserts periodic checks to detect and correct CPU faults using majority voting, which essentially requires three copies of each instruction and leads to high performance overheads. As SIMD technology can operate simultaneously on several copies of the data, it appears to be a good candidate for decreasing these overheads. To verify this hypothesis, we propose ELZAR, a compiler framework that transforms unmodified multithreaded applications to support triple modular redundancy using Intel AVX extensions for vectorization. Our experience with several benchmark suites and real-world case-studies yields mixed results: while SIMD may be beneficial for some workloads, e.g., CPU-intensive ones with many floating-point operations, it exposes higher overhead than ILR in many applications we tested.
Registers, Synchronization, Redundancy, Transient analysis, Transforms, Fault tolerant systems
D. Kuvaiskii, O. Oleksenko, P. Bhatotia, P. Felber and C. Fetzer, "ELZAR: Triple Modular Redundancy Using Intel AVX (Practical Experience Report)," 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Toulouse, France, 2016, pp. 646-653.