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2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN) (2008)
Anchorage, AK USA
June 24, 2008 to June 27, 2008
ISBN: 978-1-4244-2397-2
TABLE OF CONTENTS

Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor (Abstract)

Hisashige Ando , Fujitsu Ltd., Japan
Ryuji Kan , Fujitsu Ltd., Japan
Yoshiharu Tosaka , Fujitsu Laboratories, Japan
Keiji Takahisa , Research Center for Nuclear Physics, Osaka University, Japan
Kichiji Hatanaka , Research Center for Nuclear Physics, Osaka University, Japan
pp. 62-69
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