2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) (2004)
June 28, 2004 to July 1, 2004
J. Xu , North Carolina State University
R. K. Iyer , University of Illinois at Urbana-Champaign
Z. Kalbarczyk , University of Illinois at Urbana-Champaign
N. Nakka , University of Illinois at Urbana-Champaign
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE), which is implemented as an integral part of a modern microprocessor. The RSE interacts with the processor through an input/output interface. The CHECK instruction, a special extension of the instruction set architecture of the processor, is the interface of the application with the RSE. The detection mechanisms described here in detail are: (1) the Memory Layout Randomization (MLR) module, which randomizes the memory layout of a process in order to foil attackers who assume a fixed system layout, (2) the Data Dependency Tracking (DDT) module, which tracks the dependencies among threads of a process and maintains checkpoints of shared memory pages in order to rollback the threads when an offending (potentially malicious) thread is terminated, and (3) the Instruction Checker module (ICM), which checks an instruction for its validity or the control-flow of the program just as the instruction enters the pipeline for execution. Performance simulations for the studied modules indicate low overhead of the proposed solutions.
J. Xu, R. K. Iyer, Z. Kalbarczyk, N. Nakka, "An Architectural Framework for Providing Reliability and Security Support", 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), vol. 00, no. , pp. 585, 2004, doi:10.1109/DSN.2004.1311929