High-Speed, Area-Efficient, FPGA-Based Elliptic Curve Cryptographic Processor over NIST Binary Fields
2015 IEEE International Conference on Data Science and Data Intensive Systems (DSDIS) (2015)
Dec. 11, 2015 to Dec. 13, 2015
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSDIS.2015.44
In this paper we propose a high-performance FPGA-based implementation of an elliptic curve cryptographic (ECC) processor over binary field GF(2m) for modern cryptographic applications. A high-speed elliptic curve scalar multiplier (ECSM) is designed using an efficient finite-field arithmetic unit, where ECSM is the main operation of an ECC processor. It has been implemented in an affine coordinate system using a polynomial basis. The implemented design is synthesized in field-programmable gate array (FPGA) technology. The ECSM time in a modern Xilinx Kintex-7 FPGA is 2.66 ms at 255.66 MHz and 5.54 ms at 251.98 MHz for the field size of GF(2233) and GF(2283) respectively. Simulation results show that the implemented design is area-efficient, as it contains only 3016 slices for the field F2233 and 4625 slices for the field F2283. To the best of the authors' knowledge, the proposed ECC processor shows better performance than the available hardware implementations.
Elliptic curve cryptography, Elliptic curves, Hardware, Field programmable gate arrays
M. S. Hossain, E. Saeedi and Y. Kong, "High-Speed, Area-Efficient, FPGA-Based Elliptic Curve Cryptographic Processor over NIST Binary Fields," 2015 IEEE International Conference on Data Science and Data Intensive Systems (DSDIS), Sydney, Australia, 2015, pp. 175-181.