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2015 Euromicro Conference on Digital System Design (DSD) (2015)
Madeira, Portugal
Aug. 26, 2015 to Aug. 28, 2015
ISBN: 978-1-4673-8034-8
pp: 72-78
We study three-level implementations where the first two levels represent a standard PLA form with an ANDplane and an OR-plane. This implements a 2m-output SOP. The final stage consists of m two-input programmable LUTs. The PLA outputs are paired so that the LUT outputs implement a set of m given incompletely specified functions (ISFs). Three-level structures have been studied previously, e.g. resulting in ANDOR-AND or AND-OR-XOR implementations. By using the LUT effectively, the composition of the AND-plane can be controlled to implement a PLA which has the optimum phase assignment for maximum cube sharing. For each output, we characterize the problem of all legal implementations of such a model, by defining Boolean relations that capture all the flexibility induced by the final LUT logic. The extra LUT level provides a dimension beyond simple phase assignment. We performed experiments using a Boolean relation minimizer to compare such realizations vs. SOP forms and published three-level forms, comparing areas and delays. To approximate the possible sharing in the PLA, we mapped the 2m PLA logic using SIS. We focused on experiments with two-input Boolean functions not captured by AND-OR-AND or AND-OR-XOR approaches and found good gains in many cases with affordable increases in synthesis runtimes.
Logic gates, Table lookup, Delays, Programmable logic arrays, Boolean functions, Minimization, Benchmark testing

A. Bernasconi, R. K. Brayton, V. Ciriani, G. Trucco and T. Villa, "Bi-Decomposition Using Boolean Relations," 2015 Euromicro Conference on Digital System Design (DSD), Madeira, Portugal, 2015, pp. 72-78.
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