2013 Euromicro Conference on Digital System Design (2013)
Los Alamitos, CA, USA USA
Sept. 4, 2013 to Sept. 6, 2013
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2013.129
Partial Reconfiguration is one of the most attractive features of FPGAs. This feature provides new computing possibilities, for instance we can change a part of the initial functionality after its deployment, where a complete configuration is not needed, and the total area required is reduced. However, the design of partially reconfigurable systems has been a complex task yet. This work try to facilitate the design process and proposes a new development flow, which reduces mistakes during first stages of the design and makes the building of partial reconfiguration projects easier. In addition, we provide a dedicated hardware component, which manages bit streams nd dynamic areas. This component speed up the reconfiguration time, accomplishing a speed about 180MB/s.
Field programmable gate arrays, Software, Hardware, Complexity theory, Layout, Production facilities, Engines
J. Caba, J. D. Dondo, F. Rincon, J. Barba and J. C. Lopez, "Development Flow for FPGA-Based Scalable Reconfigurable Systems," 2013 Euromicro Conference on Digital System Design(DSD), Los Alamitos, CA, USA USA, 2013, pp. 666-669.