2013 Euromicro Conference on Digital System Design (2013)
Los Alamitos, CA, USA USA
Sept. 4, 2013 to Sept. 6, 2013
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2013.49
This paper presents hardware solution for runtime computation of loop constraints and synchronizing delays for multiple inner loops in parallel distributed implementation of digital signal processing sub-systems. Methods to map and generate the runtime computation code for loop constraints and synchronizing delays are also presented. Compared to the traditional methods, the proposed solution achieves 55% average code compaction and 32.7% average performance improvement. The solution has modest hardware cost that increases linearly with the dimension of the architecture and has no performance penalty. Results from multiple realistic examples are presented, analyzed and compared to the traditional methods.
Runtime, Indexes, Delays, Registers, Synchronization, Digital signal processing, Compaction,Code compaction, Streaming address generation, CGRA, Inner loop acceleration
Nasim Farahini, Ahmed Hemani, Kolin Paul, "Distributed Runtime Computation of Constraints for Multiple Inner Loops", 2013 Euromicro Conference on Digital System Design, vol. 00, no. , pp. 389-395, 2013, doi:10.1109/DSD.2013.49