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2011 14th Euromicro Conference on Digital System Design (2011)
Oulu, Finland
Aug. 31, 2011 to Sept. 2, 2011
ISBN: 978-0-7695-4494-6
pp: 479-486
Debugging is one of the major bottlenecks in the current VLSI design process as design size and complexity increase. Efficient automation of debugging procedures helps to reduce debugging time and to increase diagnosis accuracy. This work proposes an approach for automating the design debugging procedures by integrating SAT-based debugging with test bench based verification. The diagnosis accuracy increases by iterating debugging and counterexample generation, i.e., the total number of fault candidates decreases. The experimental results show that our approach is as accurate as exact formal debugging in 71% of the experiments.
automated debugging, testbench, diagnostic trace

A. Sülflow, G. Fey and M. Dehbashi, "Automated Design Debugging in a Testbench-Based Verification Environment," 2011 14th Euromicro Conference on Digital System Design(DSD), Oulu, Finland, 2011, pp. 479-486.
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