High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs
2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (2010)
Sept. 1, 2010 to Sept. 3, 2010
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2010.96
The work reported in this paper describes the steps given towards an FPGA-based implementation of evolvable wavelet transforms for image compression in embedded systems. An Evolutionary Algorithm (EA) for the design and optimization of the transform coefficients is tailored for a suitable System on Chip implementation. Several cut downs on the computing requirements have been done to the original algorithm, adapting it for the FPGA implementation. What this paper addresses more specifically is the validation of the algorithm using fixed point arithmetic for the whole optimization process. The results show how high quality transforms are evolved from scratch with limited precision arithmetic. Also, preliminary results of the implementation in an FPGA device are included.
R. Salvador, F. Moreno, L. Sekanina and T. Riesgo, "High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs," 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools(DSD), Lille, France, 2010, pp. 96-103.