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2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (2009)
Patras, Greece
Aug. 27, 2009 to Aug. 29, 2009
ISBN: 978-0-7695-3782-5
pp: 773-780
INDEX TERMS
logic synthesis, multi-level synthesis, 2-SPP circuit, Boolean function decomposition
CITATION

A. Bernasconi, T. Villa, V. Ciriani and G. Trucco, "Logic Minimization and Testability of 2SPP-P-Circuits," 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools(DSD), Patras, Greece, 2009, pp. 773-780.
doi:10.1109/DSD.2009.131
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