2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (2008)
Sept. 3, 2008 to Sept. 5, 2008
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2008.123
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay techniques. We discovered that a filter cache,traditionally used for reducing active power, can help reduce also leakage. The key idea is to reduce the lifetime of the lines that are in high-power state inside a leakage-saving cache. Power consumption has become one of the main concerns for designers, together with the performance. Caches account for the largest fraction of on-chip transistors in most modern processors. Therefore, they are a primary candidate for attacking the problem of the leakage. In average with the proposed solution, for instruction cache 24% improvement in leakage savings and 1.5% in IPC (Instruction Per Cycle) can be achieved with respect to drowsy cache. For data caches, 5% and 5.4% improvement can be achieved respectively. Experiments have been performed also with decay cache showing fewer benefits.
Cache decay, drowsy cache, filter cache, low power
P. Bennati and R. Giorgi, "Reducing Leakage through Filter Cache," 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools(DSD), vol. 00, no. , pp. 334-341, 2008.