The Community for Technology Leaders
2013 Euromicro Conference on Digital System Design (2007)
Lubeck, Germany
Aug. 29, 2007 to Aug. 31, 2007
ISBN: 0-7695-2978-X
TABLE OF CONTENTS
Introduction

Committees (PDF)

pp. xiii
Keynote Papers

Design Without Borders (PDF)

Jan M. Rabaey , University of California at Berkeley
pp. 3
Invited Papers

Short Distance Wireless, Dense Networks, and Their Opportunities (PDF)

David Chen , University of California at Berkeley
Nathan Pletcher , University of California at Berkeley
Simone Gambini , University of California at Berkeley
Y.H. Chee , University of California at Berkeley
Michael Mark , University of California at Berkeley
Luca de Nardis , University of California at Berkeley
Davide Guermandi , University of California at Berkeley
Jan M. Jan M. Rabaey , University of California at Berkeley
pp. 7

Error-Aware Design (Abstract)

Stanley Cheng , University of California, Irvine
Mohammad Makhzan , University of California, Irvine
Amin K. Djahromi , University of California, Irvine
Fadi Kurdahi , University of California, Irvine
Ahmed Eltawil , University of California, Irvine
pp. 8-15
Session T1 - Systems-on-a-Chip/in-a-Package

An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models (Abstract)

M. Pedram , University of Southern California
S. Hessabi , Sharif University of Technology, Tehran, Iran
M. Mirza-Aghatabar , Sharif University of Technology, Tehran, Iran
S. Koohi , Sharif University of Technology, Tehran, Iran
pp. 19-26

A FPGA Optimised Digital Real-Time Mutichannel Correlator Architecture (Abstract)

C. Jakob , Dublin Institute of Technology
A. Th. Schwarzbacher , Dublin Institute of Technology
B. Hoppe , University of Applied Science Darmstadt
R. Peters , R&D, ALV-GmbH, Langen
pp. 35-42

Design and Implementation of a 50MHZ DXT CoProcessor (Abstract)

Mohammad Amin Amiri , Iran University of Sci. and Technology
Mojdeh Mahdavi , Islamic Azad University, Iran
Reza Ebrahimi Atani , Iran University of Sci. and Technology
Sattar Mirzakuchaki , Iran University of Sci. and Technology
pp. 43-50

A resource optimized Processor Core for FPGA based SoCs (Abstract)

Christian Hochberger , Dresden University of Technology
Gerald Hempel , Dresden University of Technology
pp. 51-58

Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture (Abstract)

Rainer G. Spallek , Institute of Computer Engineering, Technische Universitat Dresden, Germany
Peter Reichel , Institute of Computer Engineering, Technische Universitat Dresden, Germany
Martin Zabel , Institute of Computer Engineering, Technische Universitat Dresden, Germany
Thomas B. Preuber , Institute of Computer Engineering, Technische Universitat Dresden, Germany
pp. 59-62

Decoupling of Computation and Communication with a Communication Assist (Abstract)

Arno Moonen , University of Technology, Eindhoven, The Netherlands
Jef van Meerbergen , Philips Research, Eindhoven, The Netherlands
Rene van den Berg , NXP Semiconductors, The Netherlands
Marco Bekooij , NXP Semiconductors, The Netherlands
pp. 63-68
Session T2 - Programmable/Re-Configurable Architectures

An Implementation of an Address Generator Using Hash Memories (Abstract)

Munehiro Matsuura , Kyushu Institute of Technology
Tsutomu , Kyushu Institute of Technology
pp. 69-76

Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor (Abstract)

Peter Sobe , University of Lubeck
Volker Hampel , University of Lubeck
Erik Maehle , University of Lubeck
pp. 77-84

Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction (Abstract)

Mark G. Arnold , Lehigh University
Panagiotis D. Vouzis , Lehigh University
Sylvain Collange , Ecole Normale Superieure de Lyon
pp. 85-93

An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector (Abstract)

Pasquale Corsonello , DEIS - University of Calabria
Stefania Perri , DEIS - University of Calabria
Paolo Zicari , DEIS - University of Calabria
Emanuele Sciagura , DEIS - University of Calabria
pp. 102-108

A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography (Abstract)

Indranil Sen Gupta , Indian Institute of Technology
Dipanwita Roy Chowdhury , Indian Institute of Technology
Santosh Ghosh , Indian Institute of Technology
Monjur Alam , Indian Institute of Technology
pp. 109-115

Fault Handling in FPGAs and Microcontrollers in Safety-Critical Embedded Applications: A Comparative Survey (Abstract)

Falk Salewski , RWTH Aachen University, Germany
Adam Taylor , Selex Sensors and Airborne Systems Basildon, SS14 3EL, UK
pp. 124-131

Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition (Abstract)

Mircea Vladuþiu , University of Timisoara
Oana Boncalo , University of Timisoara
Alexandru Amaricai , University of Timisoara
Lucian Prodan , University of Timisoara
Mihai Udrescu , University of Timisoara
pp. 132-137

A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator (Abstract)

R. Beckert , Fraunhofer IIS, Design Automation Division
W. Hardt , Chemnitz University of Technology
T. Fuchs , Fraunhofer IIS, Design Automation Division
St. Ruelke , Fraunhofer IIS, Design Automation Division
pp. 147-150

A Serial Logarithmic Number System ALU (Abstract)

Panagiotis D. Vouzis , Lehigh University
Mark G. Arnold , Lehigh University
pp. 151-156
Session T3 - System, Hardware and Embedded Software Specification, Modeling and Validation

Functional Test-Case Generation by a Control Transaction Graph for TLM Verification (Abstract)

Siamak Mohammadi , Electrical and Computer Engineering, University of Tehran, Tehran, Iran
Mohammad Reza Kakoee , Azad University, Damavand Branch, Tehran, Iran
M.H Neishaburi , Electrical and Computer Engineering, University of Tehran, Tehran, Iran
pp. 157-164

An Embedded Implementation of the Microsoft Common Language Infrastructure (Abstract)

Joey C. Libby , University of New Brunswick
Kenneth B. Kent , University of New Brunswick
pp. 165-172

Evaluating the Model Accuracy in Automated Design Space Exploration (Abstract)

Timo D. Hamalainen , Tampere University of Technology, Institute of Digital and Computer Systems
Mikko Setala , Tampere University of Technology, Institute of Digital and Computer Systems
Kalle Holma , Tampere University of Technology, Institute of Digital and Computer Systems
Erno Salminen , Tampere University of Technology, Institute of Digital and Computer Systems
pp. 173-180

P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applications (Abstract)

Ismail Assayad , VERIMAG, Centre Equation, 2 Ave Vignate, 38610 Gieres, France
Sergio Yovine , VERIMAG, Centre Equation, 2 Ave Vignate, 38610 Gieres, France
pp. 181-188

Latency Minimization for Synchronous Data Flow Graphs (Abstract)

T. Basten , Eindhoven University of Technology
A.H. Ghamarian , Eindhoven University of Technology
M.C.W. Geilen , Eindhoven University of Technology
B.D. Theelen , Eindhoven University of Technology
S. Stuijk , Eindhoven University of Technology
pp. 189-196

On Complexity of Internal and External Equivalence Checking (Abstract)

Kanupriya Gulati , Texas A&M University
Eugene Goldberg , Texas A&M University
pp. 197-206

The Criteria of Functional Delay Test Quality Assessment (Abstract)

E. Bareisa , Kaunas University of Technology
V. Jusas , Kaunas University of Technology
R. Seinauskas , Kaunas University of Technology
K. Motiejunas , Kaunas University of Technology
pp. 207-214

RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip (Abstract)

Peter Pirsch , Leibniz University of Hannover, Hannover (Germany)
Guillermo Paya-Vay , Leibniz University of Hannover, Hannover (Germany)
Javier Martin-Langerwerf , Leibniz University of Hannover, Hannover (Germany)
pp. 215-221

Functional Verification of RTL Designs driven by Mutation Testing metrics (Abstract)

Youssef Serrestou , LCIS-INPG, 50 rue Barthélémy de Laffemas, 26902 cedex, Valence
Vincent Beroulle Chantal Robach , LCIS-INPG, 50 rue Barthélémy de Laffemas, 26902 cedex, Valence
pp. 222-227

Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism (Abstract)

Peter Poplavko , Magma Design Automation, Eindhoven, Netherlands
Twan Basten , Eindhoven University of Technology, Netherlands
Jef van Meerbergen , Eindhoven University of Technology, Netherlands
pp. 228-235

A New Framework for Design and Simulation of Complex Hardware/Software Systems (Abstract)

L. Frigerio , Politecnico di Milano - Milano, Italy
D. Crespi , Politecnico di Milano - Milano, Italy
C. Brandolese , Politecnico di Milano - Milano, Italy
F. Salice , Politecnico di Milano - Milano, Italy
pp. 236-243

A DRAM Precharge Policy Based on Address Analysis (Abstract)

Chiyuan Ma , National University of Defense Technology
Shuming Chen , National University of Defense Technology
pp. 244-248

High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process (Abstract)

Per Per Larsson-Edefors , Chalmers University of Technology, SE-412 96 Gothenburg, Sweden
Mindaugas Dra¡zd¡ziulis , Chalmers University of Technology, SE-412 96 Gothenburg, Sweden
Minh Q. Do , Chalmers University of Technology, SE-412 96 Gothenburg, Sweden
pp. 249-256

Controller Design and Verification for A Pipeline Image Processor based on An Extended Petri net (Abstract)

Katsumi Wasaki , Shinshu University
Tamotsu Hayashi , Shinshu University
Toshiaki Harai , Shinshu University
Kenichi Arai , Shinshu University
pp. 257-260

Power Estimation of Time Variant SoCs with TAPES (Abstract)

Johannes Zeppenfeld , Institute for Integrated Systems, Technische Universität München
Andreas Lankes , Institute for Integrated Systems, Technische Universität München
Thomas Wild , Institute for Integrated Systems, Technische Universität München
pp. 261-264

Component-Based Hardware/Software Co-Simulation (Abstract)

Fei Xie , Portland State University
Ping Hang Cheung , Portland State University
Kecheng Hao , Portland State University
pp. 265-270
Session T4 - System, Hardware and Embedded Software Synthesis

Toggle Equivalence Preserving (TEP) Logic Optimization (Abstract)

Eugene Goldberg , Cadence Design Systems
Sunil Khatri , Texas A&M University
Kanupriya Gulati , Texas A&M University
pp. 271-279

Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology
Jon T. Butler , Naval Postgraduate School
Shinobu Nagayama , Hiroshima City University
pp. 280-287

Graph Matching Constraints for Synthesis with Complex Components (Abstract)

Ana Fuentes Martínez , Lund University, Sweden
Krzysztof Kuchcinski , Lund University, Sweden
pp. 288-295

OOCE: Object-Oriented Communication Engine for SoC Design (Abstract)

Juan C. Lopez , University of Castilla-La Mancha, Ciudad Real, Spain
Francisco Moya , University of Castilla-La Mancha, Ciudad Real, Spain
Jesús Barba , University of Castilla-La Mancha, Ciudad Real, Spain
Fernando Rincón , University of Castilla-La Mancha, Ciudad Real, Spain
David Villa , University of Castilla-La Mancha, Ciudad Real, Spain
Felix J. Villanueva , University of Castilla-La Mancha, Ciudad Real, Spain
Julio Dondo , University of Castilla-La Mancha, Ciudad Real, Spain
pp. 296-302

Timing- / Power-Optimization for Digital Logic Based on Standard Cells (Abstract)

H. Rossmann , Catena Software GmbH, Frankfurt / Oder
H. T. Vierhaus , Brandenburg University of Technology, Cottbus
S. Misera , Catena Software GmbH, Frankfurt / Oder
pp. 303-306

Energy Based Design Space Exploration of Multiprocessor VLIW Architectures (Abstract)

Neeraj Goel , Indian Institute of Technology Delhi
M. Balaksrishnan , Indian Institute of Technology Delhi
Manoj Gupta , Universitat Politecnica de Catalunya
Mayank Gupta , Veveo Inc.
pp. 307-310

Reducing the Overhead of Real-Time Operating System through Reconfigurable Hardware (Abstract)

Yunmo Chung , Kyung Hee University, Yong-in, Korea
Sang Hoon Hong , Kyung Hee University, Yong-in, Korea
Moonvin Song , Kyung Hee University, Yong-in, Korea
pp. 311-316
Session T5 - Emerging Technologies, System Paradigms and Design Methodologies

Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration (Abstract)

Joel Porquet , Universit Pierre et Marie Curie
Josep Llosa , Universitat Politecnica de Catalunya
Kolin Paul , IIT Delhi
pp. 317-324

A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects (Abstract)

M.B. Srinivas , International Institute of Information Technology (IIIT)
J.V.R. Ravindra , International Institute of Information Technology (IIIT)
pp. 325-330

A New Class of Cellular Automata (Abstract)

Jon C. Muzio , University of Victoria
Lin Sun , University of Victoria
Hosna Jabbari , University of British Columbia
pp. 331-338

Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis (Abstract)

Morteza Saheb Zamani , Amirkabir University of Technology, Computer Engineering Department, Tehran, Iran
Mehdi Sedighi , Amirkabir University of Technology, Computer Engineering Department, Tehran, Iran
Mehdi Saeedi , Amirkabir University of Technology, Computer Engineering Department, Tehran, Iran
pp. 339-346

Analysis of Variable Reordering on the QMDD Representation of Quantum Circuits (Abstract)

Kenneth B. Kent , University of New Brunswick
Sharon Van Schaick , University of New Brunswick
pp. 347-352
Session T6 - Applications of (Embedded) Digital Systems

Merge Logic for Clustered Multithreaded VLIW Processors (Abstract)

Josep Llosa , Universitat Politecnica de Catalunya, Spain
Fermin Sanchez , Universitat Politecnica de Catalunya, Spain
Manoj Gupta , Universitat Politecnica de Catalunya, Spain
pp. 353-360

Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems (Abstract)

Pierangelo Terreni , University of Pisa
Luca Fanucci , University of Pisa
Sergio Saponara , University of Pisa
Nicola E. L'Insalata , University of Pisa
pp. 361-368

Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes (Abstract)

Luca Fanucci , University of Pisa
Giuseppe Gentile , University of Pisa
Massimo Rovini , University of Pisa
pp. 369-375

FPGA/DSP-based Configurable Multi-Channel Counter (Abstract)

D. Audino , Universita di Pisa
R. Saletti , Universita di Pisa
R. Roncella , Universita di Pisa
F. Baronti , Universita di Pisa
A. Lazzeri , Universita di Pisa
pp. 376-382

Design and Implementation of a 90nm Low bit-rate Image Compression Core (Abstract)

Giuseppe Cocorullo , University of Calabria, Italy
Pasquale Corsonello , University of Calabria, Italy
Giovanni Staino , University of Calabria, Italy
Marco Lanuzza , University of Calabria, Italy
Stefania Perri , University of Calabria, Italy
pp. 383-389

FATTY: A Reliable FAT File System (Abstract)

Liu Kejia , Shanghai Jiao Tong University
Guan Haibing , Shanghai Jiao Tong University
Li Xiaoyong , Shanghai Jiao Tong University
Liang Alei , Shanghai Jiao Tong University
pp. 390-395

Proving Completeness of Properties in Formal Verification of Counting Heads for Railways (Abstract)

Rolf Drechsler , University of Bremen, 28359 Bremen, Germany
Sebastian Kinder , University of Bremen, 28359 Bremen, Germany
pp. 396-403

Architecture Exploration of 3D Video Recorder Using Virtual Platform Models (Abstract)

Juha Pekka Soinimen , VTT Technical Research Centre of Finland
Janne Vatjus Anttila , VTT Technical Research Centre of Finland
Matti Etelapera , VTT Technical Research Centre of Finland
pp. 404-411

FPGA-based Road Traffic Videodetector (Abstract)

Miroslaw Jablonski , AGH University of Science and Technology
Jaromir Przybylo , AGH University of Science and Technology
Marek Gorgon , AGH University of Science and Technology
Piotr Pawlik , AGH University of Science and Technology
pp. 412-419

Safety and Security-driven Design of Networked Embedded Systems (Abstract)

Roman Trchalik , Brno University of Technology
Miroslav Sveda , Brno University of Technology
pp. 420-423

MPSoC memory optimization for digital camera applications (Abstract)

B. Girodias , Ecole Polytechnique de Montreal
Y. Bouchebaba , STMicroelectronics
G. Nicolescu , Ecole Polytechnique de Montreal
B. Lavigueur , STMicroelectronics
P. G. Paulin , STMicroelectronics
pp. 424-427

Architecture of a Small Low-Cost Satellite (Abstract)

D. Del Corso , Politecnico di Torino, Dipartimento di Elettronica
M. Borri , Politecnico di Torino, Dipartimento di Elettronica
S. Speretta , Politecnico di Torino, Dipartimento di Elettronica
C. Sansoe , Politecnico di Torino, Dipartimento di Elettronica
L. M. Reyneri , Politecnico di Torino, Dipartimento di Elettronica
M. Tranchero , Politecnico di Torino, Dipartimento di Elettronica
C. Passerone , Politecnico di Torino, Dipartimento di Elettronica
pp. 428-431

FPGA Accelerating Algorithms of Active Shape Model in People Tracking Applications (Abstract)

Qiang Dou , National University of Defence Technology
Junfeng Li , National University of Defence Technology
Xingming Zhou , National University of Defence Technology
Yong Dou , National University of Defence Technology
Jinbo Xu , National University of Defence Technology
pp. 432-435

A Sliced Coprocessor for Native Clifford Algebra Operations (Abstract)

A. Gentile , Universita degli Studi di Palermo
C.A. Hung , Universita degli Studi di Palermo
F. Sorbello , Universita degli Studi di Palermo
S. Vitabile , Universita degli Studi di Palermo
S. Impastato , Universita degli Studi di Palermo
G. Vassallo , Universita degli Studi di Palermo
M. Grimaudo , Universita degli Studi di Palermo
S. Franchini , Universita degli Studi di Palermo
pp. 436-439

A Hardware-Software Platform for Design and Verification of In-Motorcycle Electronic Systems (Abstract)

F. Baronti , University of Pisa, via Caruso 16, 56122 Pisa, Italy
F. Lenzi , University of Pisa, via Caruso 16, 56122 Pisa, Italy
R. Saletti , University of Pisa, via Caruso 16, 56122 Pisa, Italy
R. Roncella , University of Pisa, via Caruso 16, 56122 Pisa, Italy
pp. 440-443
Special Session SS1 - Resource Aware Sensor Network Systems

Evaluating Energy Consumption in Wireless Sensor Networks Applications (Abstract)

Agustin Barberis , Universita di Genova - DIBE, Via All' Opera Pia 11 A 16145 - Genoa - Italy
Maurizio Valle , Universita di Genova - DIBE, Via All' Opera Pia 11 A 16145 - Genoa - Italy
Leonardo Barboni , Universita di Genova - DIBE, Via All' Opera Pia 11 A 16145 - Genoa - Italy
pp. 455-462

Simulation Based Verification of Energy Storage Architectures for Higher Class Tags supported by Energy Harvesting Devices (Abstract)

M. Pistauer , CISC Semiconductor Design+Consulting GmBH, Austria
Ch. Trummer , Graz University of Technology Austria
Ch. Steger , Graz University of Technology Austria
J. Preishuber-Pfluegl , CISC Semiconductor Design+Consulting GmBH, Austria
A. Janek , Graz University of Technology Austria
R. Weiss , Graz University of Technology Austria
pp. 463-462

Adaptive Distance Estimation and Localization in WSN using RSSI Measures (Abstract)

Falko Dressler , University of Erlangen
Abdalkarim Awad , University of Erlangen
Thorsten Frunzke , University of Erlangen
pp. 471-478

A Proposal of New Join Operators for Sensor Network Databases (Abstract)

Changhwa Kim , Kangnung National University, Korea
Sangkyung Kim , Kangnung National University, Korea
Seungjae Lee , Kangnung National University, Korea
pp. 479-484

A Wireless Sensor Node Architecture Using Remote Power Charging, for Interaction Applications (Abstract)

Adam Postula , University of Queensland
Matthew D'Souza , University of Queensland
Konstanty Bialkowski , University of Queensland
Montserrat Ros , University of Wollongong
pp. 485-494
Special Session SS2 - Advanced Issues of Networks-on-Chip

GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors (Abstract)

Ulrich Ruckert , University of Paderborn, Germany
Jorg-Christian Niemann , Johannes Heidenhain GmbH Traunreut, Germany
Christoph Puttmann , University of Paderborn, Germany
Mario Porrmann , University of Paderborn, Germany
pp. 495-502

On network-on-chip comparison (Abstract)

Timo D. Hamalainen , Tampere University of Technology, P.O. Box 553, FIN-33101 Tampere, Finland
Ari Kulmala , Tampere University of Technology, P.O. Box 553, FIN-33101 Tampere, Finland
Erno Salminen , Tampere University of Technology, P.O. Box 553, FIN-33101 Tampere, Finland
pp. 503-510

Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy (Abstract)

Axel Jantsch , ECS - KTH - Royal Institute of Technology, Sweden
Mikael Millberg , ECS - KTH - Royal Institute of Technology, Sweden
pp. 511-518

Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer (Abstract)

G. Falconeri , STMicroelectronics
D. Mangano , STMicroelectronics
C. Pistritto , STMicroelectronics
A. Scandurra , STMicroelectronics
pp. 519-526

Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures (Abstract)

Jochen Zimmermann , FZI Forschungszentrum Informatik
Timo Schonwald , FZI Forschungszentrum Informatik
Oliver Bringmann , FZI Forschungszentrum Informatik
Wolfgang Rosenstiel , Universitat Tubingen
pp. 527-534

On-Chip Verification of NoCs Using Assertion Processors (Abstract)

Masoud Daneshtalab , University of Tehran, Tehran, Iran
Saeed Safari , University of Tehran, Tehran, Iran
M.H Neishaburi , University of Tehran, Tehran, Iran
Mohammad Reza Kakoee , University of Tehran, Tehran, Iran
Zainalabedin Navabi , University of Tehran, Tehran, Iran
pp. 535-538

Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations (Abstract)

Cristina Silvano , Politecnico di Milano, Italy
Mariagiovanna Sami , Politecnico di Milano, Italy
Leandro Fiorin , University of Lugano
pp. 539-542

NoC Topologies Exploration based on Mapping and Simulation Models (Abstract)

Riccardo Locatelli , General Sciences TEI-Crete, Heraklion, Crete, Grece
Miltos Grammatikakis , General Sciences TEI-Crete, Heraklion, Crete, Grece
Luciano Bononi , University of Bologna
Marcello Coppola , General Sciences TEI-Crete, Heraklion, Crete, Grece
Nicola Concer , University of Bologna
pp. 543-546

Application-Specific Topology Design Customization for STNoC (Abstract)

Giovanni Mariani , University of Lugano
Gianluca Palermo , Politecnico di Milano
Marcello Coppola , STMicroelectronics
Riccardo Locatelli , STMicroelectronics
Cristina Silvano , Politecnico di Milano
pp. 547-550

Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip (Abstract)

Jouni Isoaho , University of Turku
Hannu Tenhunen , Turku Centre for Computer Science (TUCS)
Pekka Rantala , University of Turku
pp. 551-555

On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs (Abstract)

Giovanni Busonera , University of Cagliari, Italy
Paolo Meloni , University of Cagliari, Italy
Luigi Raffo , University of Cagliari, Italy
Salvatore Carta , University of Cagliari, Italy
pp. 556-562
Special Session SS3 - Dependability and Testing of Digital Systems

On the Construction of Small Fully Testable Circuits with Low Depth (Abstract)

Anna Bernasconi , University of Pisa
Gorschwin Fey , University of Bremen
Valentina Ciriani , University of Milano
Rolf Drechsler , University of Bremen
pp. 563-569

Fault Injection Techniques and their Accelerated Simulation in SystemC (Abstract)

Heinrich Theodor Vierhaus , Brandenburg University of Technology Cottbus
Silvio Misera , Brandenburg University of Technology Cottbus
André Sieber , Brandenburg University of Technology Cottbus
pp. 587-595

Hybrid BIST Optimization Using Reseeding and Test Set Compaction (Abstract)

Helena Kruus , Tallinn University of Technology, Tallinn, Estonia
Raimund Ubar , Tallinn University of Technology, Tallinn, Estonia
Gert Jervan , Tallinn University of Technology, Tallinn, Estonia
Elmet Orasson , Tallinn University of Technology, Tallinn, Estonia
pp. 596-603

Fault Diagnosis in Integrated Circuits with BIST (Abstract)

Sergei Kostin , Tallinn University of Technology
Jaan Raik , Tallinn University of Technology
Raimund Ubar , Tallinn University of Technology
Teet Evartson , Tallinn University of Technology
Harri Lensen , Tallinn University of Technology
pp. 604-610

Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties (Abstract)

Zdenek Kotasek , Brno University of Technology
Tomas Herrman , Brno University of Technology
Jaroslav Skarvada , Brno University of Technology
pp. 611-618

An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits (Abstract)

Shaahin Hessabi , Sharif University of Technology, Tehran, IRAN
Elham K. Moghaddam , Sharif University of Technology, Tehran, IRAN
pp. 619-625

Test Controller Synthesis Constrained by Circuit Testability Analysis (Abstract)

Josef Strnadel , Brno University of Technology
Richard Ruzicka , Brno University of Technology
pp. 626-633

Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment (Abstract)

Mihai Udrescu , University of Timisoara
Lucian Prodan , University of Timisoara
Mircea Vladuþiu , University of Timisoara
Oana Boncalo , University of Timisoara
Alexandru Amaricai , University of Timisoara
pp. 634-640

Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault Environment (Abstract)

Christian J. Hescott , University of Minnesota
Drew C. Ness , University of Minnesota
David J. Lilja , University of Minnesota
pp. 641-648

A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor (Abstract)

M. Marshall , University of Newcastle upon Tyne, UK
G. Russell , University of Newcastle upon Tyne, UK
pp. 649-656

Pseudo-Random Pattern Generator Design for Column-Matching BIST (Abstract)

Petr Fiser , Czech Technical University
pp. 657-663

Hierarchical Identification of Untestable Faults in Sequential Circuits (Abstract)

Jaan Raik , Tallinn University of Technology
Raimund Ubar , Tallinn University of Technology
Anna Krivenko , Tallinn University of Technology
Margus Kruus , Tallinn University of Technology
pp. 668-671

The importance of At-Speed Scan Testing: an industrial experience (Abstract)

M. Giardi , AustriaMicroSystems AG, Tobelbaderstrasse 30
L. Di Piro , AustriaMicroSystems AG, Tobelbaderstrasse 30
P. D'Abramo , AustriaMicroSystems AG, Tobelbaderstrasse 30
H. Fabian , AustriaMicroSystems AG, Tobelbaderstrasse 30
F. Baronti , University of Pisa
R. Roncella , University of Pisa
R. Saletti , University of Pisa
pp. 672-675

Online Protocol Testing for FPGA Based Fault Tolerant Systems (Abstract)

Jiri Tobola , Brno University of Technology
Zdenek Kotasek , Brno University of Technology
Tomas Martinek , Brno University of Technology
Martin Straka , Brno University of Technology
Jan Korenek , Brno University of Technology
pp. 676-679

Performance Evaluation of Instruction Set Extensions for Long Integer Modular Arithmetic on a SPARC V8 Processor (Abstract)

Johann Großschädl , Graz University of Technology, Austria
Stefan Tillich , Graz University of Technology, Austria
Alexander Szekely , Graz University of Technology, Austria
pp. 680-689
Author Index

Author Index (PDF)

pp. 690
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