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2013 Euromicro Conference on Digital System Design (2007)
Lubeck, Germany
Aug. 29, 2007 to Aug. 31, 2007
ISBN: 0-7695-2978-X
pp: 132-137
Mircea Vladuþiu , University of Timisoara
Oana Boncalo , University of Timisoara
Alexandru Amaricai , University of Timisoara
Lucian Prodan , University of Timisoara
Mihai Udrescu , University of Timisoara
ABSTRACT
This paper proposes a novel approach for increasing the performance of the floating point addition, by efficiently exploiting both paths from the classical double path adder. Thus, it becomes possible to execute two floating point additions simultaneously using a single adder, each on a different path. Performing two floating point additions in this manner will requires duplication of the signs and exponent computation modules. The cost estimates show a 20% increase of the active area for the proposed adder compared with other floating point adders. In terms of performance, the latency of the proposed adder is slightly higher with respect to other double path adders. However, the increased latency is compensated by the increased throughput obtained.
INDEX TERMS
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CITATION
Mircea Vladuþiu, Oana Boncalo, Alexandru Amaricai, Lucian Prodan, Mihai Udrescu, "Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition", 2013 Euromicro Conference on Digital System Design, vol. 00, no. , pp. 132-137, 2007, doi:10.1109/DSD.2007.54
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