Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition
10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) (2007)
Aug. 29, 2007 to Aug. 31, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2007.54
Alexandru Amaricai , University of Timisoara
Mircea Vladuþiu , University of Timisoara
Lucian Prodan , University of Timisoara
Mihai Udrescu , University of Timisoara
Oana Boncalo , University of Timisoara
This paper proposes a novel approach for increasing the performance of the floating point addition, by efficiently exploiting both paths from the classical double path adder. Thus, it becomes possible to execute two floating point additions simultaneously using a single adder, each on a different path. Performing two floating point additions in this manner will requires duplication of the signs and exponent computation modules. The cost estimates show a 20% increase of the active area for the proposed adder compared with other floating point adders. In terms of performance, the latency of the proposed adder is slightly higher with respect to other double path adders. However, the increased latency is compensated by the increased throughput obtained.
M. Vladuþiu, O. Boncalo, A. Amaricai, L. Prodan and M. Udrescu, "Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition," 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)(DSD), Lubeck, Germany, 2007, pp. 132-137.