10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) (2007)
Aug. 29, 2007 to Aug. 31, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2007.53
Volker Hampel , University of Lubeck
Peter Sobe , University of Lubeck
Erik Maehle , University of Lubeck
In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented to characterize the performance of the coprocessor in terms of computation bandwidth, latency, and the hardware-software interaction. For comparison, software based R/S encoding implementations are presented and evaluated as well. Finally, the performance of the hardware accelerated encoding is compared to a software based system.
P. Sobe, V. Hampel and E. Maehle, "Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor," 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)(DSD), Lubeck, Germany, 2007, pp. 77-84.