Message fromthe Program Chair (PDF)

Conference Committees (PDF)

The Challenges for High Performance Embedded Systems (Abstract)

Digital RF (PDF)

Deep Sub-100 nm Design Challenges (Abstract)

New Directions in Mobile Device Architectures (Abstract)

Robustness in SOC Design (Abstract)

Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication (Abstract)

Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication (Abstract)

On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures (Abstract)

Partition Based Dynamic 2D HW Multitasking Management (Abstract)

Global Analysis of Resource Arbitration for MPSoC (Abstract)

Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering (Abstract)

Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA (Abstract)

Multi-Bank Main Memory Architecture with Dynamic Voltage Frequency Scaling for System Energy Optimization (Abstract)

A Monitoring-Aware Network-on-Chip Design Flow (Abstract)

A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing (Abstract)

A Hardware IP-Core for Information Retrieval (Abstract)

Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems (Abstract)

Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors (Abstract)

Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods (Abstract)

Dependable Design for FPGA Based on Duplex System and Reconfiguration (Abstract)

A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks (Abstract)

An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n) (Abstract)

Application Specific Instruction Set Processor for Adaptive Video Motion Estimation (Abstract)

Novel Modulo 2^n + 1 Multipliers (Abstract)

Embedded Parallel Systems Based on Dynamic Look-Ahead Reconfiguration in Redundant Communication Resources (Abstract)

BCB: A Buffered CrossBar Switch Fabric Utilizing Shared Memory (Abstract)

Design and Application of a Scalable Embedded Systems? Architecture with an FPGA Based Operating Infrastucture (Abstract)

Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis (Abstract)

Adapting EPIC Architecture?s Register Stack for Virtual Stack Machines (Abstract)

Dual-Mode Quadruple Precision Floating-Point Adder (Abstract)

Adaptive High-End Microprocessor for Power-Performance Efficiency (Abstract)

Profiling Bluetooth and Linux on the Xilinx Virtex II Pro (Abstract)

A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table (Abstract)

A Computation Core for Communication Refinement of Digital Signal Processing Algorithms (Abstract)

Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW (Abstract)

An Asynchronous PLA with Improved Security Characteristics (Abstract)

Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information (Abstract)

A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems (Abstract)

A Mixed Language Fault Simulation of VHDL and SystemC (Abstract)

FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar (Abstract)

A Flexible, Syntax Independent Representation (SIR) for System Level Design Models (Abstract)

Prototyping Parallel FDTD Programs by Macro Data Flow Graph Analysis (Abstract)

VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems (Abstract)

Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems* (Abstract)

Transition Fault Test Reuse (Abstract)

Abstract Application Modeling for System Design Space Exploration (Abstract)

Characterization of the EMC Performances of the CAN Bus in a Typical System Bus Architecture for Small Satellites (Abstract)

Utilising Evolutionary Approaches and Object Oriented Techniques for Design Space Exploration (Abstract)

High-Level Decision Diagram based Fault Models for Targeting FSMs (Abstract)

Cascade Scheme for Concurrent Errors Detection (Abstract)

Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications (Abstract)

DRedSOP: Synthesis of a New Class of Regular Functions (Abstract)

Multi-objective Optimal FSM State Assignment (Abstract)

Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCs (Abstract)

A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization (Abstract)

Rachael SPARC: An Open Source 32-bit Microprocessor Core for SoCs (Abstract)

Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart (Abstract)

Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes (Abstract)

Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography (Abstract)

Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard (Abstract)

A Power-Aware Technique for Functional Units in High-Performance Processors (Abstract)

Automata Construct with Genetic Algorithm (Abstract)

ATOMI II - Framework for Easy Building of Object-oriented Embedded Systems (Abstract)

A RISC Processor with Redundant LNS Instructions (Abstract)

State Assignment for Detecting Erroneous Transitions in Finite State Machines (Abstract)

Memory Generation and Power Distribution In SOC (Abstract)

A Graph Based Algorithm for Data Path Optimization in Custom Processors (Abstract)

Testability Estimation Based on Controllability and Observability Parameters (Abstract)

Performance Improvement for H.264 Video Encoding using ILP Embedded Processor (Abstract)

Function Call Optimization in Behavioral Synthesis (Abstract)

Design Guides for a Correct DC Operation in RTD-based Threshold Gates (Abstract)

Layered Decoding of Non-Layered LDPC Codes (Abstract)

Design and Validation of Digital Channels for a Galileo Receiver Prototype (Abstract)

Two Architectures of a General Digit-Serial Normal Basis Multiplier (Abstract)

An Embedded Architecture for Mission Control of Unmanned Aerial Vehicles (Abstract)

Design of a Low-Power Digital Core for Passive UHF RFID Transponder (Abstract)

A Portable System for Measuring Human Body Movement (Abstract)

Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core (Abstract)

Clock-Gating in FPGAs: A Novel and Comparative Evaluation (Abstract)

Improving Delivery Ratio and Power Efficiency in Unicast Geographic Routing with a Realistic Physical Layer for Wireless Sensor Networks (Abstract)

Opportunistic Pervasive Computing with Domain-Oriented Virtual Machines (Abstract)

Lifetime Analysis in Heterogeneous Sensor Networks (Abstract)

Wireless Medical Information System Network for Patient ECG Monitoring (Abstract)

Voltage Sensors for Supply Capacitor in Passive UHF RFID Transponders (Abstract)

Improved Precision of Coarse Grained Localization in Wireless Sensor Networks (Abstract)

A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip (Abstract)

Adaptive Power Management for the On-Chip Communication Network (Abstract)

Packetizing OCP Transactions in the MANGO Network-on-Chip (Abstract)

Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip (Abstract)

A High Level Power Model for the Nostrum NoC (Abstract)

Off-Line Testing of Delay Faults in NoC Interconnects (Abstract)

Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads (Abstract)

Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm (Abstract)

Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions (Abstract)

Author Index (PDF)