The Community for Technology Leaders
2013 Euromicro Conference on Digital System Design (2006)
Cavtat near Dubrovnik, Croatia
Aug. 30, 2006 to Sept. 1, 2006
ISBN: 0-7695-2609-8
TABLE OF CONTENTS
Introduction

Conference Committees (PDF)

pp. xiii-xiv
Keynote Papers

The Challenges for High Performance Embedded Systems (Abstract)

Marc Duranton , Philips Research, The Netherlands
pp. 3-7

Digital RF (PDF)

Roman Staszewski , Texas Instruments, USA
pp. 8

Deep Sub-100 nm Design Challenges (Abstract)

Tohru Furuyama , Toshiba Corp., Japan
pp. 9-16
Invited Papers

Robustness in SOC Design (Abstract)

Klaus Waldschmidt , J.W. Goethe-Universitat Frankfurt am Main, Germany
pp. 27-36
SessionT12

Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication (Abstract)

Ingo Sander , Royal Institute of Technology, Sweden
Zhonghai Lu , Royal Institute of Technology, Sweden
Axel Jantsch , Royal Institute of Technology, Sweden
pp. 37-44

Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication (Abstract)

Twan Basten , Eindhoven University of Technology, The Netherlands
Amir Hossein Ghamarian , Eindhoven University of Technology, The Netherlands
Bart Theelen , Eindhoven University of Technology, The Netherlands
Marc Geilen , Eindhoven University of Technology, The Netherlands
Sander Stuijk , Eindhoven University of Technology, The Netherlands
pp. 45-52

On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures (Abstract)

Pascal Gomez , Université P& M Curie, France
Alain Greiner , Université P& M Curie, France
Fr?d?ric P?trot , TIMA, France
pp. 53-60

Partition Based Dynamic 2D HW Multitasking Management (Abstract)

Julio Septien , Universidad Complutense de Madrid, Spain
Hortensia Mecha , Universidad Complutense de Madrid, Spain
Sara Roman , Universidad Complutense de Madrid, Spain
Daniel Mozos , Universidad Complutense de Madrid, Spain
pp. 61-70
SessionT13

Global Analysis of Resource Arbitration for MPSoC (Abstract)

Jef van Meerbergen , Eindhoven University of Technology, The Netherlands
Akash Kumar , Eindhoven University of Technology, The Netherlands
Henk Corporaal , Eindhoven University of Technology, The Netherlands
Ha Yajun , National University of Singapore, Singapore
Bart Mesman , Eindhoven University of Technology, The Netherlands
pp. 71-78

Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA (Abstract)

Marko H?nnik?inen , Tampere University of Technology, Finland
Ari Kulmala , Tampere University of Technology, Finland
Timo D. H?m?l?inen , Tampere University of Technology, Finland
pp. 83-88
SessionT14

Multi-Bank Main Memory Architecture with Dynamic Voltage Frequency Scaling for System Energy Optimization (Abstract)

Michel Auguin , Signaux et Syst?mes de Sophia-Antipolis, France
C?cile Belleudy , Signaux et Syst?mes de Sophia-Antipolis, France
Hanene Ben Fradj , Signaux et Syst?mes de Sophia-Antipolis, France
pp. 89-96

A Monitoring-Aware Network-on-Chip Design Flow (Abstract)

Calin Ciordas , Eindhoven University of Technology, The Netherlands
Kees Goossens , Philips Research Laboratories Eindhoven, The Netherlands
Twan Basten , Eindhoven University of Technology, The Netherlands
Andreas Hansson , Eindhoven University of Technology, The Netherlands
pp. 97-106
SessionT15

A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing (Abstract)

C. Wolinski , Campus Universitaire de Beaulieu, France
Maya Gokhale , Los Alamos National Lab, USA
F. Charot , Campus Universitaire de Beaulieu, France
Jan R. Frigo , Los Alamos National Lab, USA
Reid B. Porter , Los Alamos National Lab, USA
C. Wagner , Campus Universitaire de Beaulieu, France
pp. 107-115

A Hardware IP-Core for Information Retrieval (Abstract)

Michael Freeman , University of York, UK
Thimal Jayasooriya , University of York, UK
pp. 115-122

Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems (Abstract)

Pedro Trancoso , University of Cyprus, Cyprus
Kyriakos Stavrou , University of Cyprus, Cyprus
pp. 123-126

Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods (Abstract)

Martin Delvai , Vienna University of Technology, Austria
Andreas Steininger , Vienna University of Technology, Austria
pp. 131-138
SessionT21

Dependable Design for FPGA Based on Duplex System and Reconfiguration (Abstract)

Pavel Kubal? , Czech Technical University in Prague, Czech Republic
Hana Kub?tov? , Czech Technical University in Prague, Czech Republic
Radek Dobi? , Czech Technical University in Prague, Czech Republic
pp. 139-145

A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks (Abstract)

Giuseppe Baruffa , Universit? degli Studi di Perugia, Italy
Lucia Bissi , Universit? degli Studi di Perugia, Italy
Pisana Placidi , Universit? degli Studi di Perugia, Italy
Andrea Scorzoni , Universit? degli Studi di Perugia, Italy
pp. 146-154
SessionT22

An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n) (Abstract)

R.V. Kamala , International Institute of Information Technology, India
M.B. Srinivas , International Institute of Information Technology, India
M. Sudhakar , International Institute of Information Technology, India
pp. 155-159

Application Specific Instruction Set Processor for Adaptive Video Motion Estimation (Abstract)

T. Dias , INESC-ID, Portugal
L. Sousa , INESC-ID, Portugal
N. Roma , INESC-ID, Portugal
S. Momcilovic , INESC-ID, Portugal
pp. 160-167

Novel Modulo 2^n + 1 Multipliers (Abstract)

H. T. Vergos , University of Patras, Greece
C. Efstathiou , TEI of Athens, Greece
pp. 168-175

Embedded Parallel Systems Based on Dynamic Look-Ahead Reconfiguration in Redundant Communication Resources (Abstract)

Eryk Laskowski , Polish Academy of Sciences, Poland
Marek Tudruj , Polish Academy of Sciences, Poland
pp. 176-179

BCB: A Buffered CrossBar Switch Fabric Utilizing Shared Memory (Abstract)

George Kornaros , Technical University of Crete, Greece
pp. 180-188
SessionT23

Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis (Abstract)

J?r?mie Detrey , ?cole Normale Sup?rieure de Lyon, France
Sylvain Collange , ?cole Normale Sup?rieure de Lyon, France
Florent de Dinechin , ?cole Normale Sup?rieure de Lyon, France
pp. 197-203

Adapting EPIC Architecture?s Register Stack for Virtual Stack Machines (Abstract)

Jamel Tayeb , University of Valenciennes, France
Smail Niar , University of Valenciennes, France
pp. 204-210
SessionT24

Dual-Mode Quadruple Precision Floating-Point Adder (Abstract)

Ahmet Akkas , Koc University, Turkey
pp. 211-220

Profiling Bluetooth and Linux on the Xilinx Virtex II Pro (Abstract)

Filipa Duarte , Delft University of Technology, The Netherlands
Stephan Wong , Delft University of Technology, The Netherlands
pp. 229-235

A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table (Abstract)

Viay Holimath , University of Santiago de Compostela, Spain
Javier Bruguera , University of Santiago de Compostela, Spain
pp. 236-239

A Computation Core for Communication Refinement of Digital Signal Processing Algorithms (Abstract)

Sylvain Huet , Universit? de Bretagne Sud, France
Olivier Pasquier , Polytech?Nantes, France
Emmanuel Casseau , Universit? de Bretagne Sud, France
pp. 240-250
SessionT25

Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW (Abstract)

Martin St?va , Czech Technical University in Prague, Czech Republic
Ondrej Nov? , Czech Technical University in Prague, Czech Republic
pp. 251-256

An Asynchronous PLA with Improved Security Characteristics (Abstract)

Simon Moore , University of Cambridge, UK
Petros Oikonomakos , University of Cambridge, UK
pp. 257-264

Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information (Abstract)

Giovanni Busonera , University of Cagliari, Italy
Salvatore Carta , University of Cagliari, Italy
Luigi Raffo , University of Cagliari, Italy
Andrea Marongiu , University of Cagliari, Italy
pp. 265-268

A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems (Abstract)

Roberto R. Osorio , University of Santiago de Compostela, Spain
Javier D. Bruguera , University of Santiago de Compostela, Spain
pp. 269-274
SessionT31

A Mixed Language Fault Simulation of VHDL and SystemC (Abstract)

Andr? Sieber , Brandenburg University of Technology Cottbus, Germany
Lars Breitenfeld , Brandenburg University of Technology Cottbus, Germany
Heinrich Theodor Vierhaus , Brandenburg University of Technology Cottbus, Germany
Silvio Misera , Brandenburg University of Technology Cottbus, Germany
pp. 275-279

FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar (Abstract)

Ouassila Labbani , Universite des sciences et technologies de Lille, France
Philippe Marquet , Universite des sciences et technologies de Lille, France
Jean-Luc Dekeyser , Universite des sciences et technologies de Lille, France
Sebastien Le Beux , Universite des sciences et technologies de Lille, France
pp. 280-287

A Flexible, Syntax Independent Representation (SIR) for System Level Design Models (Abstract)

Ines Viskic , University of California, Irvine, USA
Rainer Domer , University of California, Irvine, USA
pp. 288-294

Prototyping Parallel FDTD Programs by Macro Data Flow Graph Analysis (Abstract)

Adam Smyk , Polish-Japanese Institute of Information Technology, Poland
Marek Tudruj , Polish-Japanese Institute of Information Technology, Poland
pp. 295-304
SessionT32

VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems (Abstract)

Antonio N? , University of Las Palmas de Gran Canaria, Spain
Pedro P. Carballo , University of Las Palmas de Gran Canaria, Spain
Luz Garc? , University of Las Palmas de Gran Canaria, Spain
Armando S?nchez-Pe? , University of Las Palmas de Gran Canaria, Spain
pp. 305-312

Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems* (Abstract)

Viacheslav Izosimov , Link?ping University, Sweden
Zebo Peng , Link?ping University, Sweden
Petru Eles , Link?ping University, Sweden
Paul Pop , Link?ping University, Sweden
pp. 313-322
SessionT33

Transition Fault Test Reuse (Abstract)

R. Seinauskas , Kaunas University of Technology, Lithuania
V. Jusas , Kaunas University of Technology, Lithuania
K. Motiejunas , Kaunas University of Technology, Lithuania
E. Bareisa , Kaunas University of Technology, Lithuania
pp. 323-330

Abstract Application Modeling for System Design Space Exploration (Abstract)

Ludovic Apvrille , GET/ENST, France
Rabea Ameur-Boulifa , GET/ENST, France
Sophie Coudert , GET/ENST, France
Renaud Pacalet , GET/ENST, France
Muhammad Waseem , GET/ENST, France
pp. 331-337

Characterization of the EMC Performances of the CAN Bus in a Typical System Bus Architecture for Small Satellites (Abstract)

Luca Fanucci , Univerity of Pisa, Italy
Michele Apuzzo , Univerity of Pisa, Italy
Gianluca Casarosa , AOES BV, Italy
Bruno Sarti , European Space Agency, Italy
pp. 338-345

Utilising Evolutionary Approaches and Object Oriented Techniques for Design Space Exploration (Abstract)

Liam Noonan , University of Limerick, Ireland
Colin Flanagan , University of Limerick, Ireland
pp. 346-352
SessionT34

High-Level Decision Diagram based Fault Models for Targeting FSMs (Abstract)

Jaan Raik , Tallinn University of Technology, Estonia
Raimund Ubar , Tallinn University of Technology, Estonia
Taavi Viilukas , Tallinn University of Technology, Estonia
pp. 353-358

Cascade Scheme for Concurrent Errors Detection (Abstract)

Ilya Levin , Tel Aviv University, Israel
Vladimir Sinelnikov , Bar Ilan University, Israel
Vladimir Ostrovsky , Tel Aviv University, Israel
Osnat Keren , Bar Ilan University, Israel
pp. 359-368
SessionT40

Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications (Abstract)

Petr Fiser , Czech Technical University, Czech Republic
Hana Kub?tov? , Czech Technical University, Czech Republic
pp. 369-376

DRedSOP: Synthesis of a New Class of Regular Functions (Abstract)

Valentina Ciriani , University of Milano, Italy
Anna Bernasconi , University of Pisa, Italy
pp. 377-384

Multi-objective Optimal FSM State Assignment (Abstract)

Dominik Gawlowski , Eindhoven University of Technology, The Netherlands
Lech J?zwiak , Eindhoven University of Technology, The Netherlands
Aleksander Slusarczyk , Eindhoven University of Technology, The Netherlands
pp. 385-396
SessionT41

Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCs (Abstract)

Lech J?zwiak , Eindhoven University of Technology, The Netherlands
Sien-An Ong , Nokia Research Center
pp. 397-406

A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization (Abstract)

Roberto R. Osorio , University of Santiago de Compostela, Spain
Javier D. Bruguera , University of Santiago de Compostela, Spain
pp. 407-414

Rachael SPARC: An Open Source 32-bit Microprocessor Core for SoCs (Abstract)

Michael Cowell , University of Queensland, Australia
Adam Postula , University of Queensland, Australia
pp. 415-422

Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart (Abstract)

J. Lanchares , Complutense U. of Madrid, Spain
O. Garnica , Complutense U. of Madrid, Spain
J. M. Colmen , Complutense U. of Madrid, Spain
J. I. Hidalgo , Complutense U. of Madrid, Spain
S. Lopez , Complutense U. of Madrid, Spain
G. Mi?ana , Complutense U. of Madrid, Spain
pp. 423-432
SessionT42

Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes (Abstract)

H. T. Vierhaus , Brandenburg University of Technology Cottbus
C. Galke , Brandenburg University of Technology Cottbus
U. G?tzschmann , Brandenburg University of Technology Cottbus
pp. 433-438

Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography (Abstract)

Jacques J.A. Fournier , University of Cambridge, UK
Simon Moore , University of Cambridge, UK
pp. 439-446

Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard (Abstract)

Arno M. Wellink , University of Twente, The Netherlands
Johan Slagman , University of Twente, The Netherlands
Kenneth C. Rovers , University of Twente, The Netherlands
Michel G.J. Lammertink , University of Twente, The Netherlands
Arjan C. Dam , University of Twente, The Netherlands
pp. 447-455

A Power-Aware Technique for Functional Units in High-Performance Processors (Abstract)

Jos? Manuel Colmenar , CES Felipe II, Spain
Guadalupe Mi?ana , Universidad Complutense de Madrid, Spain
Juan Lanchares , Universidad Complutense de Madrid, Spain
Jos? Ignacio Hidalgo , Universidad Complutense de Madrid, Spain
Oscar Garnica , Universidad Complutense de Madrid, Spain
pp. 456-459

Automata Construct with Genetic Algorithm (Abstract)

M?ria J?nesov? , Czech Technical University, Czech Republic
V?t F?bera , Czech Technical University, Czech Republic
Vlastimil J?nes , Czech Technical University, Czech Republic
pp. 460-463

ATOMI II - Framework for Easy Building of Object-oriented Embedded Systems (Abstract)

Juha R?ning , University of Oulu, Finland
Tero Vallius , University of Oulu, Finland
pp. 464-474
SessionT43

A RISC Processor with Redundant LNS Instructions (Abstract)

Mark G. Arnold , Lehigh University, USA
pp. 475-482

State Assignment for Detecting Erroneous Transitions in Finite State Machines (Abstract)

Markus Damm , J.W. Goethe-Universitat Frankfurt am Main, Germany
pp. 483-490

Memory Generation and Power Distribution In SOC (Abstract)

Qing K. Zhu , SanDisk Corporation, USA
pp. 491-495

A Graph Based Algorithm for Data Path Optimization in Custom Processors (Abstract)

Jelena Trajkovic , University of California, Irvine, USA
Daniel Gajski , University of California, Irvine, USA
Bita Gorjiara , University of California, Irvine, USA
Mehrdad Reshadi , University of California, Irvine, USA
pp. 496-503

Testability Estimation Based on Controllability and Observability Parameters (Abstract)

Zden?ek Kotasek , Brno University of Technology, Czech Republic
Tomas Pe?cenka , Brno University of Technology, Czech Republic
Lukas Sekanina , Brno University of Technology, Czech Republic
Josef Strnadel , Brno University of Technology, Czech Republic
pp. 504-514
SessionT51

Function Call Optimization in Behavioral Synthesis (Abstract)

Shinya Honda , Nagoya University, Japan
Yuko Hara , Nagoya University, Japan
Hiroaki Takada , Nagoya University, Japan
Hiroyuki Tomiyama , Nagoya University, Japan
pp. 522-529

Design Guides for a Correct DC Operation in RTD-based Threshold Gates (Abstract)

Mar?a J. Avedillo , Centro Nacional de Microelectr?nica, Spain
Juan N? , Centro Nacional de Microelectr?nica, Spain
Jos? M. Quintana , Centro Nacional de Microelectr?nica, Spain
pp. 530-536
SessionT61

Layered Decoding of Non-Layered LDPC Codes (Abstract)

Luca Fanucci , University of Pisa, Italy
Massimo Rovini , University of Pisa, Italy
Nicola L?Insalata, , University of Pisa, Italy
Francesco Rossi , University of Pisa, Italy
Pasquale Ciao , University of Pisa, Italy
pp. 537-544

Design and Validation of Digital Channels for a Galileo Receiver Prototype (Abstract)

Massimo Rovini , University of Pisa, Italy
Luca Fanucci , University of Pisa, Italy
Francesco Rossi , University of Pisa, Italy
pp. 545-549

Two Architectures of a General Digit-Serial Normal Basis Multiplier (Abstract)

Martin Novotn? , CTU FEE Prague, Czech Republic
Jan Schmidt , CTU FEE Prague, Czech Republic
pp. 550-553

An Embedded Architecture for Mission Control of Unmanned Aerial Vehicles (Abstract)

J. Lopez , Technical University of Catalonia, Spain
E. Pastor , Technical University of Catalonia, Spain
P. Royo , Technical University of Catalonia, Spain
pp. 554-560
SessionT62

Design of a Low-Power Digital Core for Passive UHF RFID Transponder (Abstract)

Paolo Ciapolini , University of Parma, Italy
Ilaria De Munari , University of Parma, Italy
Andrea Ricci , University of Parma, Italy
Matteo Grisanti , University of Parma, Italy
pp. 561-568

A Portable System for Measuring Human Body Movement (Abstract)

R. Gandolfi , University of Pavia, Italy
R. Lombardi , University of Pavia, Italy
A. Cristiani , University of Pavia, Italy
G. M. Bertolotti , University of Pavia, Italy
pp. 569-576

Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core (Abstract)

Timo Alho , Tampere University of Technology, Finland
Marko H?nnik?inen , Tampere University of Technology, Finland
Panu H?m?l?inen , Tampere University of Technology, Finland
Timo D. H?m?l?inen , Tampere University of Technology, Finland
pp. 577-583

Clock-Gating in FPGAs: A Novel and Comparative Evaluation (Abstract)

Yan Zhang , VTT Technical Research Centre of Finland
Aarne M?mmel? , VTT Technical Research Centre of Finland
Jussi Roivainen , VTT Technical Research Centre of Finland
pp. 584-590
Invited Papers

Opportunistic Pervasive Computing with Domain-Oriented Virtual Machines (Abstract)

M. R? , Warsaw University of Technology, Poland
A. Pruszkowski , Warsaw University of Technology, Poland
J. Domaszewicz , Warsaw University of Technology, Poland
pp. 598-605

Lifetime Analysis in Heterogeneous Sensor Networks (Abstract)

Falko Dressler , University of Erlangen-Nuremberg, Germany
Isabel Dietrich , University of Erlangen-Nuremberg, Germany
pp. 606-616
SessionWSN

Wireless Medical Information System Network for Patient ECG Monitoring (Abstract)

Matthew D?Souza , The University of Queensland, Australia
Adam Postula , The University of Queensland, Australia
Montserrat Ros , University of Wollongong, Australia
pp. 617-624

Voltage Sensors for Supply Capacitor in Passive UHF RFID Transponders (Abstract)

Juan A. Montiel-Nelson , University of Las Palmas de G.C., Spain
R. Berenguer , Centro de Estudios e Investigaciones Tecnicas de Guipuzcoa (C.E.I.T.), Spain
R. Morales-Ramos , University of Las Palmas de G.C., Spain
A. Garcia-Alonso , Centro de Estudios e Investigaciones Tecnicas de Guipuzcoa (C.E.I.T.), Spain
pp. 625-629

Improved Precision of Coarse Grained Localization in Wireless Sensor Networks (Abstract)

Dirk Timmermann , University of Rostock, Germany
Frank Reichenbach , University of Rostock, Germany
Jan Blumenthal , University of Rostock, Germany
pp. 630-640
SessionLPNOC41

A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip (Abstract)

Mikkel B. Stensgaard , Technical University of Denmark (DTU), Denmark
Jens Spars? , Technical University of Denmark (DTU), Denmark
Tobias Bjerregaard , Technical University of Denmark (DTU), Denmark
pp. 641-648

Adaptive Power Management for the On-Chip Communication Network (Abstract)

Axel Jantsch , Royal Institute of Technology, Sweden
Guang Liang , University of Amsterdam, The Netherlands
pp. 649-656

Packetizing OCP Transactions in the MANGO Network-on-Chip (Abstract)

Jens Spars? , Technical University of Denmark (DTU), Denmark
Tobias Bjerregaard , Technical University of Denmark (DTU), Denmark
pp. 657-664

Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip (Abstract)

Norbert Wehn , University of Kaiserslautern, Germany
Christian Neeb , University of Kaiserslautern, Germany
pp. 665-672

A High Level Power Model for the Nostrum NoC (Abstract)

Axel Jantsch , Royal Institute of Technology (KTH), Sweden
Sandro Penolazzi , Royal Institute of Technology (KTH), Sweden
pp. 673-676

Off-Line Testing of Delay Faults in NoC Interconnects (Abstract)

Raimund Ubar , Tallinn University of Technology, Estonia
Artur Jutman , Tallinn University of Technology, Estonia
Zebo Peng , Link?ping University, Sweden
Tomas Bengtsson , J?nk?ping University, Sweden
Shashi Kumar , J?nk?ping University, Sweden
pp. 677-680

Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads (Abstract)

Axel Jantsch , Royal Institute of Technoogy, Sweden
Ingo Sander , Royal Institute of Technoogy, Sweden
Rikard Thid , Royal Institute of Technoogy, Sweden
pp. 681-688

Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm (Abstract)

Cristian Grecu , University of British Columbia, Canada
Amlan Ganguly , Washington State University, USA
Haibo Zhu , Washington State University, USA
Partha Pratim Pande , Washington State University, USA
pp. 689-695

Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions (Abstract)

Rickard Holsmark , J?nk?ping University, Sweden
Maurizio Palesi , DIIT, University of Catania, Italy
Shashi Kumar , J?nk?ping University, Sweden
pp. 696-703
Author Index

Author Index (PDF)

pp. 704-706
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