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9th EUROMICRO Conference on Digital System Design (DSD'06) (2006)
Cavtat near Dubrovnik, Croatia
Aug. 30, 2006 to Sept. 1, 2006
ISBN: 0-7695-2609-8
pp: 577-583
Panu H?m?l?inen , Tampere University of Technology, Finland
Timo Alho , Tampere University of Technology, Finland
Marko H?nnik?inen , Tampere University of Technology, Finland
Timo D. H?m?l?inen , Tampere University of Technology, Finland
ABSTRACT
The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption hardware core suited for devices in which low cost and low power consumption are desired. The core constitutes of a novel 8-bit architecture and supports encryption with 128-bit keys. In a 0.13 ?m CMOS technology our area optimized implementation consumes 3.1 kgates. The throughput at the maximum clock frequency of 153 MHz is 121 Mbps, also in feedback encryption modes. Compared to previous 8-bit implementations, we achieve significantly higher throughput with corresponding area. The energy consumption per processed block is also lower.
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CITATION

T. Alho, M. H?nnik?inen, P. H?m?l?inen and T. D. H?m?l?inen, "Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core," 9th EUROMICRO Conference on Digital System Design (DSD'06)(DSD), Cavtat near Dubrovnik, Croatia, 2006, pp. 577-583.
doi:10.1109/DSD.2006.40
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