The Community for Technology Leaders
2013 Euromicro Conference on Digital System Design (2005)
Porto, Portugal
Aug. 30, 2005 to Sept. 3, 2005
ISBN: 0-7695-2433-8
TABLE OF CONTENTS
Introduction
Cover
Introduction
Keynote Speeches

Networks on Chip (PDF)

pp. null

Multi-media Applications and Imprecise Computation (Abstract)

Melvin A. Breuer , University of Southern California
pp. 2-7
SS2: Dependability and Testing of Digital Systems, Part 1. (S1)

BIST Technique for GALS Systems (Abstract)

Eckhard Grass , IHP, Im Technologiepark
Milos Krstic , IHP, Im Technologiepark
pp. 10-16

Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming (Abstract)

Yang Guo , National University of Defense Technology, China
GongJie Liu , National University of Defense Technology, China
Tun Li , National University of Defense Technology, China
SiKun Li , National University of Defense Technology, China
pp. 17-25
System Synthesis, Part 1. Power and Component Driven System Synthesis (S2)

P2I: An Innovative MDA Methodology for Embedded Real-Time System (Abstract)

Y. Sorel , INRIA, Rocquencourt
A. Cuccuru , LIFL,Lille FR.
T. Saunier , Thales, LJS
R. De Simone , INRIA, Sophia
G. Siegel , Esterel Technologies
pp. 26-33

Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction (Abstract)

Petru Eles , Linkoping University, Sweden
Dong Wu , University of Southampton
Bashir M. Al-Hashimi , University of Southampton
Marcus T. Schmitz , University of Southampton
pp. 34-41
Circuits Synthesis, Part 1. Arithmetic (S3)

A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation (Abstract)

Lars Bengtsson , Chalmers University of Technology
Andreas Lindahl , Chalmers University of Technology
pp. 42-47
SS2: Dependability and Testing of Digital Systems, Part 2. (S4)

Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST (Abstract)

Peter Filter , Czech Technical University
Hana Kub?tov? , Czech Technical University
pp. 56-63

Improved Fault Emulation for Synchronous Sequential Circuits (Abstract)

Jaan Raik , Tallinn University of Technology
Valentin Tihhomirov , Tallinn University of Technology
Peeter Ellervee , Tallinn University of Technology
Raimund Ubar , Tallinn University of Technology
pp. 72-78

Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs (Abstract)

Wiezlaw Kuzmicz , Warsaw University of Technology
Witold Pleskacz , Warsaw University of Technology
Raimund Ubar , Tallinn University of Technology
Jaan Raik , Tallinn University of Technology
Joachim Sudbrock , Darmstadt University of Technology
pp. 79-82

Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment (Abstract)

Petru Eles , Linkoping University, Sweden
Zebo Peng , Linkoping University, Sweden
Zhiyuan He , Linkoping University, Sweden
Gert Jervan , Linkoping University, Sweden
pp. 83-87
System Synthesis, Part 2. Component Based System Synthesis (S5)

Hardware Virtual Components Compliant with Communication System Standards (Abstract)

C. Jego , GET/ENST
N Le Heno , Turbo Concept SAS, FRANCE
B. Le Gal , LESTER Laboratory
P. Kaiffasz , Thalles Communication
E. Casseau , LESTER Laboratory
P. Bomel , LESTER Laboratory
N. Abdelli , Thalles Communication
AM Foulliart , Thalles Communication
pp. 88-95

High-Level Synthesis in Latency Insensitive System Methodology (Abstract)

N. Abdelli , Thalles Communication
P. Bomel , LESTER Laboratory
E. Boutillon , LESTER Laboratory
A-M. Fouilliart , Thalles Communication
P. Kaifasz , Thalles Communication
E. Martin , LESTER Laboratory
pp. 96-101

Embedded Object Architecture (Abstract)

Juha Roning , University of Oulu
Tero Vallius , University of Oulu
pp. 102-107

An Effective Framework for Enabling the Reuse of External Soft IP (Abstract)

Soujanna Sarkar , DSPS Group, Texas Instruments, Banglore, India
Subash G. Chandar , DSPS Group, Texas Instruments, Banglore, India
pp. 108-113
Circuits Synthesis, Part 2. Logic Synthesis (S6)

A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs (Abstract)

Jozef Kulisz , Silesian University of Technology
Adam Milik , Silesian University of Technology
Dariusz Kania , Silesian University of Technology
pp. 114-121

An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS (Abstract)

Md. Sumon Shahriar , University of Dhaka
Chowdhury Farhan Ahmed , University of Dhaka
A.R. Mustafa , Uni. Asia Pac., Bangladesh
Hafiz MD Hasan Babu , University of Dhaka
Shahed Anwar , University of Dhaka
A.N.M. Zaheduzzaman , Stamford University
Abu Ahmed Ferdaus , University of Dhaka
pp. 122-126

State Assignment for PAL-based CPLDs (Abstract)

Robert Czerwinski , Institute of Electronics, Silesian University of Technology
Dariusz Kania , Institute of Electronics, Silesian University of Technology
pp. 127-134

Coefficient Bit Reordering Method for Configurable FIR Filtering on Folded Bit-plane Array (Abstract)

Ivan Milentijevic , Faculty of Electronic Engineering, University of Nis, Serbia and Montenegro
Vladimir Ciric , Faculty of Electronic Engineering, University of Nis, Serbia and Montenegro
pp. 135-138

Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series (Abstract)

Krzysztof S. Berezowski , Wroclaw University of Technology
Sarma B. K. Vrudhula , ECE Dept. University of Arizona
pp. 139-143
SS1: Wireless Sensor Systems, Part 1. (S7)

Design of Transport Triggered Architecture Processors for Wireless Encryption (Abstract)

Marko Hannikainen , Tampere University of Technology / Institute of Digital and Computer Systems
Timo D. Hamalainen , Tampere University of Technology / Institute of Digital and Computer Systems
Jari Heikkinen , Tampere University of Technology / Institute of Digital and Computer Systems
Panu Hamalainen , Tampere University of Technology / Institute of Digital and Computer Systems
pp. 144-152

RF CMOS Circuits for Ad-Hoc Networks and Wearable Computing (Abstract)

K. Iniewski , University of Alberta
C. Siu , University of Alberta
S. Kasnavi , University of Alberta
F. Nabki , University of Alberta
pp. 153-160

Co-simulation ofWireless Local Area Network Terminals with Protocol Software Implemented in SDL (Abstract)

Petri Kukkala , Institute of Digital and Computer Systems
Timo D. Hamalainen , Institute of Digital and Computer Systems
Marko Hannikainen , Institute of Digital and Computer Systems
pp. 161-164

Optimization of Electronic Power Consumption in Wireless Sensor Nodes (Abstract)

R. Bhutada , Institute of Microsystem Technology-IMTEK
Y. Manoli , Institute of Microsystem Technology-IMTEK
S. Ramachandran , Institute of Microsystem Technology-IMTEK
S. Jayapal , Institute of Microsystem Technology-IMTEK
pp. 165-169

Vital Signs Remote Management System for PDAs (Abstract)

Edna Barros , Informatics Center
Danielly Cruz , Informatics Center
pp. 170-175
Verification Techniques, Part 1. (S8)

MA2TG: A Functional Test Program Generator for Microprocessor Verification (Abstract)

SiKun Li , National University of Defense Technology, China
Yang Guo , National University of Defense Technology, China
Dan Zhu , National University of Defense Technology, China
Tun Li , National University of Defense Technology, China
GongJie Liu , National University of Defense Technology, China
pp. 176-183

A processor for testing mixed-signal cores in System-on-Chip (Abstract)

Francisco Duarte , Universidade do Porto, INESC Porto
Jose S. Matos , Universidade do Porto, INESC Porto
J. Machado da Silva , Universidade do Porto, INESC Porto
Jose C. Alves , Universidade do Porto, INESC Porto
G. A. Pinho , Universidade do Porto, INESC Porto
pp. 184-191

Functional Test Generation Remote Tool (Abstract)

E. Bareisa , Kaunas University of Technology
V. Jusas , Kaunas University of Technology
K. Motiejunas , Kaunas University of Technology
R. Seinauskas , Kaunas University of Technology
pp. 192-195

Validation of Embedded Systems Using Formal Method Aided Simulation (Abstract)

Daniel Karlson , Linkoping Universitet, Sweden
Petru Eles , Linkoping Universitet, Sweden
Zebo Peng , Linkoping Universitet, Sweden
pp. 196-201
Application Specific Architectures, Part 1. (S9)

VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes (Abstract)

Massimo Rovini , University of Pisa
Luca Fanucci , University of Pisa
Nicola E. L?Insalata , University of Pisa
Francesco Rossi , University of Pisa
pp. 202-209

A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor (Abstract)

Luciano Volcan Agostini , GME/UFRGS - GACI/UFPel - Brazil
Sergio Bampi , GME/UFRGS - Porto Alegre - Brazil
Ivan Saraiva Silva , DIMAp/UFRN Natal - Brazil
Roger Carvalho Porto , GACI/UFPel - Brazil
pp. 210-213

Reconfigurable Parallel Approximate String Matching on FPGAs (Abstract)

Jin Hwan Park , State University of New York
pp. 214-217

Efficient MLP Digital Implementation on FPGA (Abstract)

F. Gennaro , University of Palermo
S. Vitabile , I.CA.R. - Italian National Research Council
F. Sorbello , University of Palermo
V. Conti , University of Palermo
pp. 218-222

Designing a Binary Neural Network Co-processor (Abstract)

Jim Austin , University of York
Michael Freeman , University of York
pp. 223-227

Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms (Abstract)

Hamid Noori , Amirkabir University of Technology
Hamid Safizadeh , Amirkabir University of Technology
Ali Jahanian , Amirkabir University of Technology
Mehdi Sedighi , Amirkabir University of Technology
Neda Zolfaghari , Amirkabir University of Technology
pp. 227-230

Massively Parallel Hardware Architecture for Genetic Algorithms (Abstract)

Nadia Nedjah , State University of Rio de Janeiro
Luiza de Macedo Mourelle , State University of Rio de Janeiro
pp. 231-234

Implementation of a block based neural branch predictor (Abstract)

G. Megson , The University of Reading
O. Cadenas , The University of Reading,
D. Jones , The University of Reading
pp. 235-238

PRUS - Processor Network for Digital Circuit Implementation (Abstract)

Olesya Guz , Kharkov National University of Radio Electronics
Vladimir Hahanov , Kharkov National University of Radio Electronics
Volodymyr Obrizan , Kharkov National University of Radio Electronics
Stanley Hyduke , Aldec Inc, USA
pp. 239-242

Capturing Processor Architectures from Protocol Processing Applications: a Case Study (Abstract)

Tero Nurmi , University of Turku
Seppo Virtanen , University of Turku
Jani Paakkulainen , University of Turku
pp. 243-246

Yield-aware Floorplanning (Abstract)

Maciej J. Ciesielski , University of Massachusetts
Israel Koren , University of Massachusetts
Zhaojun Wo , University of Massachusetts
pp. 247-253
SS1: Wireless Sensor Systems, Part 2. (S10)

Design of A Development Platform for HW/SW Codesign ofWireless Integrated Sensor Nodes (Abstract)

Jan Madsen , Technical University of Denmark
Andreas Vad Lorentzen , Technical University of Denmark
Phillipe Bonnet , Copenhagen University
Martin Leopold , Copenhagen University
Kashif Virk , Technical University of Denmark
pp. 254-260

An Efficient MAC Protocol for Sensor Network Considering Energy Consumption and Information Retrieval Pattern (Abstract)

Mohammad M. M. Rad , Sharif University of Technology
Babak H. Khalaj , Sharif University of Technology
Y. Ghiassi , Sharif University of Technology
Ali hesam Mohseni , Sharif University of Technology
Mohammad S Nikjoo , Sharif University of Technology
pp. 261-266

Wireless Sensor Network Implementation for Industrial Linear Position Metering (Abstract)

Timo D. Hamalainen , Tampere University of Technology
Mikko Kohvakka , Tampere University of Technology
Marko Hannikainen , Tampere University of Technology
pp. 267-275
Verification Techniques, Part 2. (S11)

MemBIST Applet for Learning Principles of Memory Testing and Generating Memory BIST (Abstract)

Martin Simlast? , Institute of Informatics, Slovak Academy of Sciences
M?ria Fischerov? , Institute of Informatics, Slovak Academy of Sciences
pp. 276-281

High-Level Modelling and Detection of the Faulty Behaviour of VOQ Switches under Balanced Traffic (Abstract)

Miguel Pereira , Intelsis Sistemas Inteligentes, S.A.
F.Javier Gonz?lez-Casta? , Department of Telematic Engineering, University of Vigo, Spain
Juan J. Rodr?guez-Andina , Department of Electronic Technology, University of Vigo, Spain
Enrique Soto , Department of Electronic Technology, University of Vigo, Spain
pp. 282-288
Application Specific Architectures, Part 2. (S12)

A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder (Abstract)

Javier D. Bruguera , Campus Sur. Santiago de Compostela
Roberto R. Osorio , Campus Sur. Santiago de Compostela
pp. 298-305

Exploring Graphics Processor Performance for General Purpose Applications (Abstract)

Maria Charalambous , Department of Computer Science, University of Cyprus
Pedro Trancoso , Department of Computer Science, University of Cyprus
pp. 306-313

Hardware-Based Implementation of the Common Approximate Substring Algorithm (Abstract)

Kenneth B. Kent , University of New Brunswick
Sharon Van Schaick , University of New Brunswick
Patricia A. Evans , University of Lethbridge
Jacqueline E. Rice , University of Lethbridge
pp. 314-321
System Synthesis, Part 3. High Level Language based System Synthesis (S13)

Cost-effective VLSI Design of Non Linear Image Processing Filters (Abstract)

Sergio Saponara , DIIEIT, University of Pisa
Stefano Marsi , DEEI, University of Trieste
Michele Cassiano , DIIEIT, University of Pisa
Riccardo Coen , DIIEIT, University of Pisa
Luca Fanucci , DIIEIT, University of Pisa
pp. 322-329

Formal Communication Semantics of SystemC^FL (Abstract)

K.L. Man , Eindhoven University of Technology
pp. 338-345

Throughput of Streaming Applications Running on a Multiprocessor Architecture (Abstract)

Nikolay Kavaldjiev , Department of EEMCS
Gerard J. M. Smit , Department of EEMCS
Pierre G. Jansen , Department of EEMCS
pp. 350-355
Reconfigurable Systems, Part 1. (S14)

A Constraints Programming Approach for Fabric Cell Synthesis (Abstract)

Christophe Wolinski , Rennes University, France
Krzysztof Kuchcinski , Lund University, Sweden
pp. 356-363

SystemC-based Design Methodology for Reconfigurable System-on-Chip (Abstract)

Juha-Pekka Soininen , VTT Electronics
Yang Qu , VTT Electronics
Kari Tiensyrja , VTT Electronics
pp. 364-371

Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems (Abstract)

Mehdi Sedighi , University, Qazvin, IRAN
Morteza Saheb Zamani , University, Qazvin, IRAN
Farhad Mehdipour , University, Qazvin, IRAN
pp. 372-378

An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems (Abstract)

Michel Auguin , University of Nice Sophia Antipolis
Benjemaa Maher , Research unit GMS, National School of Engineering of Sfax
Ghaffari Fakhreddine , University of Nice Sophia Antipolis
Abid Mohamed , Research unit GMS, National School of Engineering of Sfax
pp. 379-382

Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs (Abstract)

Miguel L. Silva , FEUP/DEEC, Spain
Jo?o Canas Ferreira , FEUP/DEEC and INESC Porto, Spain
pp. 383-387
Data Management in SoC, Part 1. (S15)

Predictable embedding of large data structures in multiprocessor networks-on-chip (Abstract)

Bart Mesman , Eindhoven University of Technology
Twan Basten , Eindhoven University of Technology
Sander Stuijk , Eindhoven University of Technology
Marc Geilen , Eindhoven University of Technology
pp. 388-396

An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures (Abstract)

M. Fernandez , Autom?tica, Universidad Complutense
F. Rivera , Autom?tica, Universidad Complutense
N. Bagherzadeh , University of California, Irvine
pp. 396-402

Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip (Abstract)

Zebo Peng , Linkopings Universitet
Petru Eles , Linkopings Universitet
Erik Larsson , Linkopings Universitet
Anders Larsson , Linkopings Universitet
pp. 403-411
SS3: Remonte Educational Tools for Design and Testing, Part 1 (S16)

An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform (Abstract)

R. Ubar , Tallinn University of Technology
J. Raik , Tallinn University of Technology
V. Vislogubov , Tallinn University of Technology
A. Jutman , Tallinn University of Technology
pp. 412-419

Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies (Abstract)

Josef Stmadel , Brno University of Technology, Czech Republic
Zdenek Kotasek , Brno University of Technology, Czech Republic
pp. 420-427

Remote Path Delay Fault Simulation (Abstract)

Einar J. Aas , Department of Electronics and Telecommunications, NTNU
Oystein Gjermundnes , Department of Electronics and Telecommunications, NTNU
pp. 428-434

Internet-Based IC Technology Design and Simulation (Abstract)

V. Nelayev , Belarusian State University of Informatics and Radioelectronics, BELARUS
K. Kudin , Belarusian State University of Informatics and Radioelectronics, BELARUS
V. Stempitsky , Belarusian State University of Informatics and Radioelectronics, BELARUS
pp. 435-441
Circuits Synthesis, Part 3. Advanced Logic Synthesis (S17)

Decomposition of Multi-Output Functions for CPLDs (Abstract)

Dariusz Kania , Institute of Electronics, Silesian University of Technology
Adam Milik , Institute of Electronics, Silesian University of Technology
Józef Kulisz , Institute of Electronics, Silesian University of Technology
pp. 442-449

High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates (Abstract)

Lech Jowiak , Eindhoven University of Technology
Szymon Bieganski , Eindhoven University of Technology
pp. 450-459

Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures (Abstract)

Pawe Tomaszewicz , Warsaw University of Technology
Mariusz Rawski , Warsaw University of Technology
Henry Selvaraj , University of Nevada, Las Vegas
Tadeusz Luba , Warsaw University of Technology
pp. 460-466

On LUT Cascade Realizations of FIR Filters (Abstract)

Takahiro Suzuki , Meiji University
Yukihiro Iguchi , Meiji University
Tsutomu Sasao , Kyushu Institute of Technology
pp. 467-475
Performance Optimization: Architecture and Tools, Part 1. (S18)

ARPA - A Technology Independent and Synthetizable System-on-Chip Model for Real-Time Applications (Abstract)

Antonio B. Ferrari , Universidade de Aveiro / IEETA
Valery A. Sklyarov , Universidade de Aveiro / IEETA
Arnaldo S. R. Oliveira , Universidade de Aveiro / IEETA
pp. 484-491

Run-time Adaptive Resources Allocation and Balancing on Nanoprocessors Arrays (Abstract)

Giuseppe Passino , DIEE - University of Cagliari
Danilo Pani , DIEE - University of Cagliari
Luigi Raffo , DIEE - University of Cagliari
pp. 492-499
Author Index

Author Index (Abstract)

pp. 500
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