The Community for Technology Leaders
2013 Euromicro Conference on Digital System Design (2004)
Rennes, France
Aug. 31, 2004 to Sept. 3, 2004
ISBN: 0-7695-2203-3
TABLE OF CONTENTS

Conference Committees (PDF)

pp. xii-xiii
Keynote Speeches

Reliability and Power Management of Integrated Systems (Abstract)

Tajana Simunic , CSL-Stanford University, Stanford, CA
Giovanni De Micheli , CSL-Stanford University, Stanford, CA
Kresimir Mihic , CSL-Stanford University, Stanford, CA
pp. 5-11

Functional Validation of Programmable Architectures (Abstract)

Prabhat Mishra , University of California, Irvine, USA
Nikil Dutt , University of California, Irvine, USA
pp. 12-19

Long Term Trends for Embedded System Design (Abstract)

Ahmed A. Jerraya , TIMA Laboratory, France
pp. 20-26

System-Level Power Optimization (Abstract)

Wolfgang Nebel , Oldenburg University and OFFIS
pp. 27-34
Invited Papers

Life-Inspired Systems (Abstract)

Lech J?zwiak , Eindhoven University of Technology, The Netherlands
pp. 36-43

Implicit vs. Explicit Resource Allocation in SMT Processors (Abstract)

Mateo Valero , DAC, UPC, Spain
Alex Ramirez , DAC, UPC, Spain
Francisco J. Cazorla , DAC, UPC, Spain
Rizos Sakellariou , University of Manchester, UK
Peter M. W. Knijnenburg , LIACS, Leiden University, the Netherlands
Enrique Fernandez , University of Las Palmas Gran Canaria, Spain
pp. 44-51
Processor and Memory Architectures (S1)

Arithmetic Coding Architecture for H.264/AVC CABAC Compression System (Abstract)

Javier D. Bruguera , University of Santiago de Compostela, Spain
Roberto R. Osorio , University of Santiago de Compostela, Spain
pp. 62-69

A Simple Micro-Threaded Data-Driven Processor (Abstract)

D. Wyland , Wyland Group
M. Singh , San Jose State University
V. Tejaswi , San Jose State University
T. Ha , San Jose State University
W. Sana , San Jose State University
A. Bindal , San Jose State University
S. Brugada , San Jose State University
pp. 70-77
Synthesis (HL, LS, PS) (S6)

A Novel Signed Higher-Radix Full-Adder Algorithm and Implementation with Current-Mode Multi-Valued Logic Circuits (Abstract)

Nizamettin Aydin , University of Edinburgh, UK
Turgay Temel , University of Edinburgh, UK
Avni Morgul , Bogazici University, Turkey
pp. 80-87

Memory Aware HLS and the Implementation of Ageing Vectors (Abstract)

Nathalie Julien , LESTER / University of South Brittany, France
Gwenol? Corre , LESTER / University of South Brittany, France
Eric Martin , LESTER / University of South Brittany, France
Eric Senn , LESTER / University of South Brittany, France
pp. 88-95
Processor and Memory Architectures (S2)

A Complete Methodology for Memory Optimization in DSP Applications (Abstract)

F. Marteil , LESTER - University of South Brittany - Lorient, France
N. Julien , LESTER - University of South Brittany - Lorient, France
E. Senn , LESTER - University of South Brittany - Lorient, France
E. Martin , LESTER - University of South Brittany - Lorient, France
pp. 98-103

ASSEC: An Asynchronous Self-Checking RISC-based Processor (Abstract)

G. Russell , University of Newcastle upon Tyne, UK
P. D. Hyde , University of Newcastle upon Tyne, UK
pp. 104-111

Compiler-Directed Dynamic Memory Disambiguation for Loop Structures (Abstract)

Chris Bailey , University of York, UK
Soyeb Alli , University of York, UK
pp. 130-134
Synthesis (HL, LS, PS) (S7)

Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary Algorithms (Abstract)

Mariusz Rawski , Warsaw University of Technology, Poland
Henry Selvaraj , University of Nevada, Las Vegas
Pawel Morawiecki , Warsaw University of Technology, Poland
pp. 136-143

Cost-Efficient Implementation of Adaptive Finite State Machines (Abstract)

Manfred Koegst , Fraunhofer Institute for Integrated Circuits
Steffen R? , Fraunhofer Institute for Integrated Circuits
Maik Boden , Fraunhofer Institute for Integrated Circuits
Jos? Luis Tiburcio Bad? , Fraunhofer Institute for Integrated Circuits
pp. 144-151

Boolean Minimizer FC-Min: Coverage Finding Process (Abstract)

Petr Fiser , Czech Technical University
Hana Kub?tov? , Czech Technical University
pp. 152-159

An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods (Abstract)

Aleksander Slusarczyk , Eindhoven University of Technology, The Netherlands
Dominik Gawlowski , Eindhoven University of Technology, The Netherlands
Lech J?zwiak , Eindhoven University of Technology, The Netherlands
pp. 160-167

BDD Circuit Optimization for Path Delay Fault Testability (Abstract)

Rolf Drechsler , University of Bremen, Germany
Goerschwin Fey , University of Bremen, Germany
Junhao Shi , University of Bremen, Germany
pp. 168-172
Applications of (Embedded) Digital Systems (S15)

A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder (Abstract)

P. Ciao , University of Pisa, Italy
L. Fanucci , IEIIT, National Research Council, Pisa, Italy
G. Colavolpe , University of Parma, Italy
pp. 174-181

VLSI Design of a Digital RFI Cancellation Scheme for VDSL Transceivers (Abstract)

L. Fanucci , IEIIT, National Research Council, Pisa, Italy
E. Petri , University of Pisa, Italy
R. Locatelli , University of Pisa, Italy
pp. 182-189

Shift Invert Coding (SINV) for Low Power VLSI (Abstract)

Damu Radhakrishnan , State University of New York, New Paltz
Jayapreetha Natesan , State University of New York, New Paltz
pp. 190-194

Generalized Analytical Model for the Design of Irregularly Shaped Power Planes and Passives in Mixed Signal Applications (Abstract)

Jayanti Venkataraman , Rochester Institute of Technology, NY
Jeffrey McFiggins , Rochester Institute of Technology, NY
Marie Yvanoff , Rochester Institute of Technology, NY
pp. 195-199

IP-Block Based Integration of Very High Performance WLAN Modem (Abstract)

Jussi Roivainen , VTT Electronics, Finland
Jukka Rautio , VTT Electronics, Finland
pp. 200-207
DSP + MISC (S17)

{\text{\{ 2}}^{\text{n}} + 1,2^{n + k} ,2^n - 1\} : A New RNS Moduli Set Extension (Abstract)

Leonel Sousa , IST/INESC-ID, Lisboa, Portugal
Ricardo Chaves , IST/INESC-ID, Lisboa, Portugal
pp. 210-217

Image Processing Algorithms on Reconfigurable Architecture using HandelC (Abstract)

Daggu Venkateshwar Rao , University of Nevada Las Vegas
V. Muthukumar , University of Nevada Las Vegas
pp. 218-226

On the Packet-Switched Implementation of a Discrete-Time CNN (Abstract)

Suleyman Malki , Lund University, Sweden
Lambert Spaanenburg , Lund University, Sweden
pp. 234-241
Special Architectures (S5)

Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs (Abstract)

Luo Jianwen , Nanyang Technological University, Singapore
Jong Ching Chuen , Nanyang Technological University, Singapore
pp. 244-248

Finite Precision Analysis of Support Vector Machine Classification in Logarithmic Number Systems (Abstract)

Faisal M. Khan , Lehigh University, Bethlehem, Pennsylvania
Mark G. Arnold , Lehigh University, Bethlehem, Pennsylvania
William M. Pottenger , Lehigh University, Bethlehem, Pennsylvania
pp. 254-261
Processor and Memory Architectures (S3)

Memory Requirement Optimization with Loop Fusion and Loop Shifting (Abstract)

Per Gunnar Kjeldsberg , Norwegian University of Science and Technology, Trondheim, Norway
Martin Palkovic , IMEC, Leuven, Belgium
Qubo Hu , Norwegian University of Science and Technology, Trondheim, Norway
pp. 272-278
Synthesis (S9)

Information Trans-Coders in Information-Driven Circuit Synthesis (Abstract)

L. J?zwiak , Eindhoven University of Technology, The Netherlands
S. Bieganski , Eindhoven University of Technology, The Netherlands
pp. 288-397

Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation. (Abstract)

J. Madsen , Technical University of Denmark
J. Spars? , Technical University of Denmark
S. F. Nielsen , Technical University of Denmark
pp. 298-305
SOC (S13)

A Constraints Programming Approach to Communication Scheduling on SoPC Architectures (Abstract)

Christophe Wolinski , IRISA, IFSIC France
Maya Gokhale , Los Alamos National Laboratory, NM, USA
Krzysztof Kuchcinski , Lund University, Sweden
pp. 308-315

Easy SoC Design with VCI SystemC Adapters (Abstract)

Salim Ouadjaout , M3Systems Inc., France
Dominique Houzet , INSA-RENNES, France
pp. 316-323
Special Architectures (S4)

Multi-Pipeline Implementations of Real-Time Vector DFT (Abstract)

Alexander A. Petrovsky , Bialystok Technical University, Poland
Sergei L. Shkredov , Belarusian State University of Informatics and, Radioelectronics (Belarus)
pp. 326-333

Pipeline-Level Control of Self-Resetting Pipelines (Abstract)

Abdel Ejnioui , University of Central Florida, Orlando, Florida
Abdelhalim Alsharqawi , University of Central Florida, Orlando, Florida
pp. 342-349

An Energy-Efficient Adaptive Multiple-Issue Architecture (Abstract)

Mars Lan , University of Auckland, New Zealand
Morteza Biglari-Abhari , University of Auckland, New Zealand
pp. 350-357

A High Speed FPGA Implementation of the Rijndael Algorithm (Abstract)

Yusuf ?. Tekmen , Middle East Technical University, Ankara, Turkey
A. Neslin Ismailglu , Tubitak-Bilten, Ankara, Turkey
Burak Okcan , Tubitak-Bilten, Ankara, Turkey
Refik Sever , Tubitak-Bilten, Ankara, Turkey
Murat Askar , Middle East Technical University, Ankara, Turkey
pp. 358-362

Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design (Abstract)

Bengt Oelmann , Mid-Sweden University, Sweden
Cao Cao , Mid-Sweden University, Sweden
pp. 363-370
Specification and Modeling (S10)

A Formal Verification Methodology for IP-based Designs (Abstract)

Zebo Peng , IDA, Link?pings universitet
Petru Eles , IDA, Link?pings universitet
Daniel Karlsson , IDA, Link?pings universitet
pp. 372-379

Diminished-1 Modulo 2^n + 1 Squarer Design (Abstract)

H. T. Vergos , University of Patras, Greece
C. Efstathiou , TEI of Athens, Greece
pp. 380-386

Handel-C implementation of Classical Component Labelling Algorithm (Abstract)

Miroslaw Jablonski , AGH University of Science and Technology, Poland
Marek Gorgon , AGH University of Science and Technology, Poland
pp. 387-393

Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA (Abstract)

Eric Martin , University of South-Brittany, France
Dominique Houzet , University of South-Brittany, France
David Ell?ouet , University of South-Brittany, France
J.-G. Cousin , University of South-Brittany, France
Nathalie Julien , University of South-Brittany, France
pp. 394-401

Mapping of High-Level SDL Models to Efficient Implementations for TinyOS (Abstract)

Jerzy Ryman , IHP, Germany
Daniel Dietterle , IHP, Germany
Kai Dombrowski , IHP, Germany
Rolf Kraemer , IHP, Germany
pp. 402-406
Validation / Verification (S12)

A Heuristic for Wiring-Aware Built-In Self-Test Synthesis (Abstract)

Petru Eles , Link?ping University, Sweden
Zebo Peng , Link?ping University, Sweden
Abdil Rashid Mohamed , Link?ping University, Sweden
pp. 408-415

The Logarithmic Checking Method for On-Line Testing of Computing Circuits for Processing of the Approximated Data (Abstract)

A. Drozd , Odessa National Polytechnic University, Ukraine
J. Drozd , Odessa National Polytechnic University, Ukraine
R. Al-Azzeh , Zarqa Private University, Jordan
M. Lobachev , Odessa National Polytechnic University, Ukraine
pp. 416-423

Scene Management Models and Overlap Tests for Tile-Based Rendering (Abstract)

B. Juurlink , Delft University of Technology, The Netherlands
P. Liuha , Nokia Research Center, Tampere, Finland
S. Vassiliadis , Delft University of Technology, The Netherlands
I. Antochi , Delft University of Technology, The Netherlands
pp. 424-431

Evaluation of Transient Fault Susceptibility in Microprocessor Systems (Abstract)

P. Gawkowski , Warsaw University of Technology
J. Sosnowski , Warsaw University of Technology
pp. 432-439

Topological BDP Fault Simulation Method (Abstract)

Stanley Hyduke , Kharkov National University of Radio Electronics
Irina Hahanova , Kharkov National University of Radio Electronics
Vladimir Hahanov , Kharkov National University of Radio Electronics
pp. 440-443

Techniques for Formal Verification of Digital Systems: A System Approach (Abstract)

Hamid Shojaei , Islamic Azad University
Habib Ghayoumi , Islamic Azad University
pp. 444-449
Applications of (Embedded) Digital Systems (S16)

Efficient Rapid Prototyping of Image and Video Processing Algorithms (Abstract)

A. Gentile , Universit? degli Studi di Palermo, Italy
F. Sorbello , Universit? degli Studi di Palermo, Italy
S. M. Siniscalchi , Universit? degli Studi di Palermo, Italy
S. Vitabile , CNR - Italian National Research Council, Palermo, Italy
pp. 452-458

FPGA Based Design of the Railway's Interlocking Equipments (Abstract)

Hana Kubatova , Czech Technical University Prague
Radek Dobias , Czech Technical University Prague
pp. 467-473
Specification and Modeling (S11)

CASSE: A System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-on-Chip (Abstract)

V?ctor Reyes , University of Las Palmas GC, Spain
Tom?s Bautista , University of Las Palmas GC, Spain
Gustavo Marrero , University of Las Palmas GC, Spain
Wido Kruijtzer , Philips Research Laboratories, The Netherlands
Pedro P. Carballo , University of Las Palmas GC, Spain
pp. 476-483

Modeling a Network Processor Using Object Oriented Techniques (Abstract)

Colin Flanagan , University of Limerick, Ireland
Liam Noonan , University of Limerick, Ireland
pp. 484-490
SOC (S14)

An Energy-Efficient Network-on-Chip for a Heterogeneous Tiled Reconfigurable Systems-on-Chip (Abstract)

Gerard J. M. Smit , University of Twente, the Netherlands
Nikolay Kavaldjiev , University of Twente, the Netherlands
pp. 492-498

Interesting Applications of Atmel AVR Microcontrollers (Abstract)

Stanislav Korbel , Czech Technical University
Vlastimil Janes , Czech Technical University
pp. 499-506
Special Architectures (S5)

A Fast and Well-Structured Multiplier (Abstract)

Jung-Yup Kang , University of Southern California
Jean-Luc Gaudiot , University of California at Irvine
pp. 508-515

Fast Reconfigurable Hardware for the M-ary Modular Exponentiation (Abstract)

Luiza de Macedo Mourelle , State University of Rio de Janeiro, Brazil
Nadia Nedjah , State University of Rio de Janeiro, Brazil
pp. 516-523

Towards New Real-Time Processor: The Multioperand MSB-First Real-Time Adder (Abstract)

Kuspriyanto , Bandung Institute of Technology
Yusrila Y. Kerlooza , Indonesian Computer University (UNIKOM)
pp. 524-529
MISC + Algorithm (S18)

Workload Simulation Method for Evaluation of Application Feasibility in a Mobile Multiprocessor Platform (Abstract)

Jari Kreku , VTT Electronics, Finland
Jani Penttil? , VTT Electronics, Finland
Janne Kangas , Nokia Mobile Phones, Finland
Juha-Pekka Soininen , VTT Electronics, Finland
pp. 532-539

An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits Design (Abstract)

Ivan Blunno , Politecnico di Torino, Italy
Guy Alain Narboni , Implexe, Marseille, France
Claudio Passerone , Politecnico di Torino, Italy
pp. 540-547

An Efficient Exponential Algorithm with Exponential Convergence Rate (Abstract)

Chichyang Chen , Feng Chia University, Taiwan
Kuo-Sheng Cheng , Feng Chia University, Taiwan
pp. 548-555

What to Adapt in a High-Performance Microprocessor (Abstract)

Pedro Trancoso , University of Cyprus
pp. 556-563
Sensor Networks (S19)

DCP: A New Data Collection Protocol for Bluetooth-Based Sensor Networks (Abstract)

Dirk Timmermann , University of Rostock
Matthias Handy , University of Rostock
Frank Grassert , University of Rostock
pp. 566-573

Hybrid Greedy/Face Routing for Ad-Hoc Sensor Network (Abstract)

L. Gewali , University of Nevada, Las Vegas
V. Muthukumar , University of Nevada, Las Vegas
H. Selvaraj , University of Nevada, Las Vegas
J. Li , University of Nevada, Las Vegas
pp. 574-578

Architecture of Wireless Sensor Node using Novel Ultra-Wideband Modulation Scheme (Abstract)

Matthew D'Souza , The University of Queensland, Australia
Adam Postula , The University of Queensland, Australia
pp. 579-586

Phased Array and Adaptive Antenna Transceivers in Wireless Sensor Networks (Abstract)

Yiannos Manoli , Albert-Ludwig-University, Germany
Ruimin Huang , Albert-Ludwig-University, Germany
pp. 587-592
Poster Papers

A Mechanism for Implementing Precise Exceptions in Pipelined Processors (Abstract)

Soyeb Alli , University of York, Heslington, York
Chris Bailey , University of York, Heslington, York
pp. 598-602

Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic (Abstract)

Mazder Rahman , University of Dhaka, Bangladesh
Moinul Islam Zaber , University of Dhaka, Bangladesh
Rafiquil Islam , University of Dhaka, Bangladesh
Hafiz Hasan Babu , University of Dhaka, Bangladesh
pp. 603-606

Dynamic Filter Cache for Low Power Instruction Memory Hierarchy (Abstract)

Saurav Bhattacharyya , Nanyang Technological University, Singapore
Thambipillai Srikanthan , Nanyang Technological University, Singapore
Kugan Vivekanandarajah , Nanyang Technological University, Singapore
pp. 607-610

Area Efficient, Low Power and Robust Design for Add-Compare-Select Units (Abstract)

Bahman Javadi , Amirkabir University of Technology
Mohammad K. Akbari , Amirkabir University of Technology
Ali Jahanian , Amirkabir University of Technology
Mohsen Naderi , Amirkabir University of Technology
pp. 611-614

A Static Low-Power, High-Performance 32-bit Carry Skip Adder (Abstract)

Michael Schulte , Sandbridge Technologies, Inc., White Plains, NY; University of Wisconsin, WI
Suman Mamidi , Sandbridge Technologies, Inc., White Plains, NY; University of Wisconsin, WI
Stamatis Vassiliadis , Delft University of Technology, The Netherlands
John Glossner , Sandbridge Technologies, Inc., White Plains, NY; Delft University of Technology, The Netherlands
Haoran Wang , Sandbridge Technologies, Inc., White Plains, NY
Pablo Balzola , Sandbridge Technologies, Inc., White Plains, NY
Kai Chirca , Sandbridge Technologies, Inc., White Plains, NY; Delft University of Technology, The Netherlands
pp. 615-619

A Novel VLSI Architecture to Implement Region Merging Algorithm for Image Segmentation (Abstract)

J. D. Kranthi Kumar , Indian Institute of Technology, Chennai
S. Srinivasan , Indian Institute of Technology, Chennai
pp. 620-623

A Threshold Logic Synthesis Tool for RTD Circuits (Abstract)

Jos? M. Quintana , Instituto de Microelectr?nica de Sevilla, CNM, Spain
Mar?a J. Avedillo , Instituto de Microelectr?nica de Sevilla, CNM, Spain
pp. 624-627

Author Index (PDF)

pp. 628-631
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