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Euromicro Symposium on Digital System Design, 2004. DSD 2004. (2004)
Rennes, France
Aug. 31, 2004 to Sept. 3, 2004
ISBN: 0-7695-2203-3
pp: 444-449
Hamid Shojaei , Islamic Azad University
Habib Ghayoumi , Islamic Azad University
ABSTRACT
In this paper we describe a methodology for the formal verification of a processor using the CTL property language. Processors are important in design and verification of digital systems because they have structures that represent most digital systems. Processors are programmable, have control parts, data parts and are rich in bus structure. Verification of CPU structures requires verification of data components, controllers, datapath and instruction level verification. This work uses a processor to discuss various features of formal verification. Because of generality of processors, we will be able to cover most aspects of property-based verification and properties used for this purpose.
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CITATION

H. Shojaei and H. Ghayoumi, "Techniques for Formal Verification of Digital Systems: A System Approach," Euromicro Symposium on Digital System Design, 2004. DSD 2004.(DSD), Rennes, France, 2004, pp. 444-449.
doi:10.1109/DSD.2004.1333309
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