The Community for Technology Leaders
2013 Euromicro Conference on Digital System Design (2003)
Belek-Antalya, Turkey
Sept. 1, 2003 to Sept. 6, 2003
ISBN: 0-7695-2003-0
TABLE OF CONTENTS
Keynote Speeches

NoCs: A new Contract between Hardware and Software (Abstract)

Axel Jantsch , Royal Institute of Technology, Stockholm, Sweden
pp. 10

Customizable Embedded Processor Architectures (Abstract)

Peter Petrov , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 468
Processor and Memory Architectures

null (PDF)

pp. null

Distance-aware L2 Cache Organizations for Scalable Multiprocessor Systems (Abstract)

Hyong-Shik Kim , Chungnam National University
Sung Woo Chung , Seoul National University
Chu Shik Jhon , Seoul National University
pp. 24

Unified Dual Data Caches (Abstract)

Ben Juurlink , Delft University of Technology
pp. 33

CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors (Abstract)

Ismail Kadayif , Pennsylvania State University
Mahmut Kandemir , Pennsylvania State University
Lin Li , Pennsylvania State University
Mary Jane Irwin , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
pp. 41
Synthesis (HL, LS, PS)

null (PDF)

pp. null

Reversible Logic Synthesis for Minimization of Full-Adder Circuit (Abstract)

Rafiqul Islam , University of Dhaka, Bangladesh
Hafiz Hasan Babu , University of Dhaka, Bangladesh
Syed Mostahed Ali Chowdhury , University of Dhaka, Bangladesh
Ahsan Raja Chowdhury , University of Dhaka, Bangladesh
pp. 50

Multi Component Digital Circuit Optimization by Solving FSM Equations (Abstract)

Maria Vetrova , Tomsk State University, Russia
Svetlana Zharikova , Tomsk State University, Russia
Nina Yevtushenko , Tomsk State University, Russia
pp. 62
Processor and Memory Architectures

null (PDF)

pp. null

DYNORA: A New Caching Technique (Abstract)

P. Srivatsan , Sri Venkateswara College of Engineering, Chennai, India
P. B. Sudarshan , Sri Venkateswara College of Engineering, Chennai, India
P. P. Bhaskaran , Sri Venkateswara College of Engineering, Chennai, India
pp. 70

Causality Constraints for Processor Architectures with Sub-Word Parallelism (Abstract)

Renate Merker , Dresden University of Technology, Germany
Rainer Schaffer , Dresden University of Technology, Germany
pp. 82

A methodology for the design of AHB bus master wrappers (Abstract)

Guy Bois , ?cole Polytechnique de Montr?al
Marc Bertola , ?cole Polytechnique de Montr?al
pp. 90
Synthesis (HL, LS, PS)

null (PDF)

pp. null

A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges (Abstract)

Winthir Brunnbauer , Institute for Integrated Circuits, TU Munich
Thomas Wild , Institute for Integrated Circuits, TU Munich
J?rgen Foag , Institute for Integrated Circuits, TU Munich
Nuria Pazos , Institute for Integrated Circuits, TU Munich
pp. 98

An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices (Abstract)

Mariusz Rawski , Warsaw University of Technology
Tadeusz Luba , Warsaw University of Technology
Henry Selvaraj , University of Nevada, Las Vegas
pp. 104
Processor and Memory Architectures

null (PDF)

pp. null

Variations on Truncated Multiplication (Abstract)

James E. Stine , Illinois Institute of Technology
Oliver M. Duverne , Illinois Institute of Technology
pp. 112

Exploring Storage Organization in ASIP Synthesis (Abstract)

Manoj Kumar Jain , Indian Institute of Technology Delhi, India
Anshul Kumar , Indian Institute of Technology Delhi, India
M. Balakrishnan , Indian Institute of Technology Delhi, India
pp. 120
Synthesis (HL, LS, PS)

null (PDF)

pp. null

A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages (Abstract)

Ling Wang , University of Nevada, Las Vegas
Henry Selvaraj , University of Nevada, Las Vegas
pp. 144

Information-driven Library-based Circuit Synthesis (Abstract)

L. J?zwiak , Eindhoven University of Technology
A. Chojnacki , PDF Solutions Inc., San Jose
S. Bieganski , Eindhoven University of Technology
pp. 148
Special Architectures

null (PDF)

pp. null

Low-power Branch Target Buffer for Application-Specific Embedded Processors (Abstract)

Peter Petrov , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 158

A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole Routing (Abstract)

Wouter Bach , Departement of Computer Science of the University of Twente
Erik Schepers , Departement of Computer Science of the University of Twente
Philip H?lzenspies , Departement of Computer Science of the University of Twente
Mischa Jonker , Departement of Computer Science of the University of Twente
Gerard Smit , Departement of Computer Science of the University of Twente
Bart Sikkes , Departement of Computer Science of the University of Twente
Paul Havinga , Departement of Computer Science of the University of Twente
pp. 166

A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator (Abstract)

F. Leporati , Universit? di Pavia
G. Danese , Universit? di Pavia
M. Bera , Universit? di Pavia
I. De Lotto , Universit? di Pavia
A. Spelgatti , Universit? di Pavia
pp. 173
System-on-a-Chip

null (PDF)

pp. null

A Novel Specification Model for IP-based Design (Abstract)

Stephan Klaus , Darmstadt University of Technology
Sorin A. Huss , Darmstadt University of Technology
pp. 190

An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures (Abstract)

Theofanis Orphanoudakis , Ellemedia Technologies
George Kornaros , Ellemedia Technologies
Nickolaos Zervos , Ellemedia Technologies
pp. 197
Special Architectures

null (PDF)

pp. null

Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization (Abstract)

S. Ramachandran , Indian Institute of Technology
S. Srinivasan , Indian Institute of Technology
pp. 206

A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors (Abstract)

Ant?nio B. Ferrari , University of Aveiro
Arnaldo Oliveira , University of Aveiro
Valery Sklyarov , University of Aveiro
Iouliia Skliarova , University of Aveiro
pp. 222

Fast Heuristics for the Edge Coloring of Large Graphs (Abstract)

Rolf Drechsler , University of Bremen
Nicole Drechsler , University of Bremen
Mario Hilgemeier , University of Bremen
pp. 230
Synthesis (HL, LS, PS)

null (PDF)

pp. null

NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables (Abstract)

Michal Pleban , Warsaw University of Technology
Henry Selvaraj , University of Nevada, Las Vegas
Piotr Sapiecha , Warsaw University of Technology
Piotr Buciak , Warsaw University of Technology
Hubert Niewiadomski , Warsaw University of Technology
Tadeusz Luba , Warsaw University of Technology
pp. 248

Design Tools and Reusable Libraries for FPGA-Based Digital Circuits (Abstract)

Pedro Almeida , University of Aveiro
Iouliia Skliarova , University of Aveiro
Valery Sklyarov , University of Aveiro
Manuel Almeida , University of Aveiro
pp. 255

HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming (Abstract)

Kia Bazargan , University of Minnesota
Karthikeyan Bhasyam , University of Minnesota
pp. 264

Reconfigurable Randomized K-way Graph Partitioning (Abstract)

Fatih Kocan , Southern Methodist University, Dallas, TX
pp. 272

Multiple Voltage and Frequency Scheduling for Power Minimization (Abstract)

Muthukumar Venkatesan , University of Nevada Las Vegas
Bharath Radhakrishnan , University of Nevada Las Vegas
pp. 279
Special Architectures

null (PDF)

pp. null

A Fast Additive Normalization Method for Exponential Computation (Abstract)

Rui-Lin Chen , Feng Chia University
Ming-Hwa Sheu , National Yunlin University of Science and Technology
Chichyang Chen , Feng Chia University
pp. 286
System-on-a-Chip (2) and Validation/Verification

null (PDF)

pp. null

Testable Design Verification Using Petri Nets (Abstract)

Richard Ruzicka , Brno University of Technology
pp. 304

Hierarchical Constraint Conscious RT-level Test Generation (Abstract)

Ozgur Sinanoglu , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 312

The Application of Formal Verification to SPW Designs (Abstract)

Behzad Akbarpour , Concordia University
Sofi?ne Tahar , Concordia University
pp. 325
Applications of (Embedded) Digital Systems

null (PDF)

pp. null

Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator Algorithm (Abstract)

Filip Traugott , Swedish Defence Material Administration
Lennart Lindh , M?lardalen University, V?ster?s, Sweden
Kim Andersson , M?lardalen University, V?ster?s, Sweden
Andreas L?fgren , RealFast Hardware Consulting AB, V?ster?s, Sweden
pp. 334

A New Algorithm for High-Speed Projection in Point Rendering Applications (Abstract)

M. B? , Univ. of Santiago de Compostela, Spain
M. Wand , Univ. of T?bingen, Germany
M. Amor , Univ. of A Coru?a, Spain
W. Strasser , Univ. of T?bingen, Germany
A. del R? , Univ. of T?bingen, Germany
pp. 338

Sensor Platform Design for Automotive Applications (Abstract)

M. De Marinis , austriamicrosystems
C. Rosadini , University of Pisa
C. Sicilia , University of Pisa
A. Renieri , University of Pisa
D. Sicilia , University of Pisa
A. Giambastiani , austriamicrosystems
L. Fanucci , IEIIT
A. Rocchi , austriamicrosystems
pp. 346
Specification and Modeling

null (PDF)

pp. null

Modelling and Simulation of a Digital IC System Using SimulPet: Application to a Speech Coding Communication IC (Abstract)

J. Mart?n-Canales , Electronics Dpt. University of M?laga
F. R?os-G?mez , Electronics Dpt. University of M?laga
R. Fern?ndez-Ramos , Electronics Dpt. University of M?laga
J. Romero-S?nchez , Electronics Dpt. University of M?laga
pp. 356

T&D-Bench+ - A Software Environment for Modeling and Simulation of State-of-the-Art Processors (Abstract)

Fl?vio Rech Wagner , Universidade Federal do Rio Grande do Sul
Sandro Neves Soares , Universidade de Caxias do Sul
pp. 362

Temperature Influence on Power Consumption and Time Delay (Abstract)

A. Golda , AGH University of Science and Technology
A. Kos , AGH University of Science and Technology
pp. 378
Applications of (Embedded) Digital Systems

null (PDF)

pp. null

A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications (Abstract)

N. Ismailoglu , Middle East Technical University
O. Benderli , Middle East Technical University
Y. ?. Tekmen , Middle East Technical University
pp. 384

null (PDF)

pp. null

Understanding Video Pixel Processing Applications for Flexible Implementations (Abstract)

Erwin Bellers , Philips Semiconductors
Marc Duranton , Philips Research
Johan Janssen , Philips Semiconductors
Selliah Rathnam , Philips Semiconductors
Om Prakash Gangwal , Philips Research
pp. 392

Power/Area Analysis and Optimization of a DS-SS receiver for an Integrated Sensor Microsystem (Abstract)

Nizamettin Aydin , University of Edinburgh
David R. S. Cumming , University of Glasgow
Tughrul Arslan , University of Edinburgh
pp. 402
Specification and Modeling

null (PDF)

pp. null

A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits (Abstract)

Akihiko Hyodo , Graduate School of Information Science and Electrical Engineering at Kyushu University
Masanori Muroyama , Graduate School of Information Science and Electrical Engineering at Kyushu University
Takanori Okuma , Graduate School of Information Science and Electrical Engineering at Kyushu University
Hiroto Yasuura , Graduate School of Information Science and Electrical Engineering at Kyushu University
pp. 408

Framed Complexity Analysis in SystemC for Multi-level Design Space Exploration (Abstract)

Armin Wellig , Advanced System Technology - STMicroelectronics, Geneva, Switzerland
Julien Zory , Advanced System Technology - STMicroelectronics, Geneva, Switzerland
pp. 416
Poster Papers

Analytical Bounds on the Threads in IXP1200 Network Processor (Abstract)

H.S. Jamadagni , Indian Institute of Science
S.T.G.S. Ramakrishna , Indian Institute of Science
pp. 426

Exact Numerical Processing (Abstract)

Higinio Mora Mora , DTIC. University Alicante, Spain
Jer?nimo Mora Pascual , DTIC. University Alicante, Spain
Juan Manuel Garc?a Chamizo , DTIC. University Alicante, Spain
pp. 434

Stochastic Reconfigurable Hardware for Neural Networks (Abstract)

Luiza de Macedo Mourelle , State University of Rio de Janeiro, Brazil
Nadia Nedjah , State University of Rio de Janeiro, Brazil
pp. 438

An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs (Abstract)

Stanislaw Deniziak , Cracow University of Technology
Krzysztof Sapiecha , Cracow University of Technology
Radoslaw Czarnecki , Cracow University of Technology
pp. 443

Distributing SoC Simulations over a Network of Computers (Abstract)

Timo D. H?m?l?inen , Tampere University of Technology
Jouni Riihim?ki , Tampere University of Technology
V?in? Helminen , Tampere University of Technology
Kimmo Kuusilinna , Tampere University of Technology
pp. 447

FC-Min: A Fast Multi-Output Boolean Minimizer (Abstract)

Petr Fiser , Czech Technical University
Hana Kubatova , Czech Technical University
Jan Hlavicka , Czech Technical University
pp. 451

A Methodology for Designing Communication Architectures for Multiprocessor SoCs (Abstract)

V?clav Dvor? , University of Technology
Vladim?r Kut?lek , University of Technology
pp. 455

Compiler-Directed Management of Instruction Accesses (Abstract)

I. Kadayif , Pennsylvania State University
G. Chen , Pennsylvania State University
G. Chen , Pennsylvania State University
M. Kandemir , Pennsylvania State University
U. Sezer , University of Wisconsin - Madison
W. Zhang , Pennsylvania State University
I. Kolcu , UMIST
pp. 459

Test scheduling for embedded systems (Abstract)

Josef Strnadel , Brno University of Technology, Czech Republic
Daniel Mika , Brno University of Technology, Czech Republic
Zdenek Kot?sek , Brno University of Technology, Czech Republic
pp. 463

Author Index (PDF)

pp. 477
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