The Community for Technology Leaders
2013 Euromicro Conference on Digital System Design (2002)
Dortmund, Germany
Sept. 4, 2002 to Sept. 6, 2002
ISBN: 0-7695-1790-0
TABLE OF CONTENTS
Introduction
Plenary — Keynote Session I
Processor and Memory Architectures

An Asynchronous Victim Cache (Abstract)

J. D. Garside , University of Manchester
D. Hormdee , University of Manchester
S. B. Furber , University of Manchester
pp. 4

Formal Verification of a DSP Chip Using an Iterative Approach (Abstract)

Ali Habibi , Concordia University
Adel Ghazel , ?cole Superieure Des Communications de Tunis
Sofiène Tahar , Concordia University
pp. 12

Enhanced Configurable Parallel Memory Architecture (Abstract)

Timo Hämäläinen , Tampere University of Technology
Eero Aho , Tampere University of Technology
Jarno Vanne , Tampere University of Technology
Kimmo Kuusilinna , Tampere University of Technology
pp. 28
Partitioning and Decomposition

Recursive Bi-Partitioning of Netlists for Large Number of Partitions (Abstract)

T. Eschbach , Albert-Ludwigs-University
R. Drechsler , University of Bremen
G. Angst , Concept Engineering GmbH
L. Linhard , Concept Engineering GmbH
W. Günther , Infineon Technologies
pp. 38

Folded Bit-Plane FIR Filter Architecture with Changeable Folding Factor (Abstract)

Teufik Tokić , University of Niš
Vladimir Ćirić , University of Niš
Ivan Milentijević , University of Niš
Oliver Vojinović , University of Niš
pp. 45

Best Polarity for Low Power XOR Gate Decomposition (Abstract)

A. E. A. Almaini , Napier University
Yinshui Xia , Napier University
pp. 53

A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design (Abstract)

J. Lanchares , Universidad Complutense de Madrid
J.I. Hidalgo , Universidad Complutense de Madrid
A. Ibarra , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
pp. 60
Special Architectures

A Flexible Architecture for H.263 Video Coding (Abstract)

Marcos Jiménez , Universidad Politécnica de Madrid
César Sanz , Universidad Politécnica de Madrid
Matias J. Garrido , Universidad Politécnica de Madrid
Juan M. Meneses , Universidad Politécnica de Madrid
pp. 70

The Synthesis of a Hardware Scheduler for Non-Manifest Loops (Abstract)

Thijs Krol , University of Twente
Egbert Molenkamp , University of Twente
Omar Mansour , University of Twente
pp. 78

Configurable Memory Organisation for Communication Applications (Abstract)

Antti Pelkonen , Technical Research Centre of Finland
Juha-Pekka Soininen , Technical Research Centre of Finland
Jussi Roivainen , Technical Research Centre of Finland
pp. 86

Enhanced Reusability for SoC-Based HW/SW Co-Design (Abstract)

Maik Boden , FhG IIS Erlangen
Klaus Feske , FhG IIS Erlangen
Steffen Rülke , FhG IIS Erlangen
Jörg Schneider , FhG IIS Erlangen
pp. 94
System Specification and Modelling

Integrating a Computational Model and a Run Time System for Image Processing on a UAV (Abstract)

Klas Nordberg , Link?ping University
Patrick Doherty , Link?ping University
Krzysztof Kuchcinski , Lunds University
Per Andersson , Lunds University
pp. 102

Specification and Simulation of Microprocessor Operations and Parallel Instructions (Abstract)

Paul Gorissen , Philips Research Laboratories Eindhoven
Loe Feijs , Eindhoven University of Technology
Joachim Trescher , Philips Research Laboratories Eindhoven
pp. 110

Integration of Instruction Set Simulators into SystemC High Level Models (Abstract)

Alex Kravtsov , Infineon Technologies AG
Ilia Oussorov , Infineon Technologies AG
Wolfgang Raab , Infineon Technologies AG
Ulrich Hachmann , Infineon Technologies AG
pp. 126
Parallel Processor Architectures

Architecture Design of a Scalable Single-Chip Multi-Processor (Abstract)

B. D. Theelen , Eindhoven University of Technology
A. C. Verschueren , Eindhoven University of Technology
pp. 132

Parallel Multimedia Processor Using Customised Infineon TriCores (Abstract)

Ari Wahyudi , Nanyang Technological University
Amos Omondi , Nanyang Technological University
pp. 140

Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches (Abstract)

Manuel Lois Anido , Federal University of Rio de Janeiro
Alexander Paar , Universit?t Karlsruhe
Nader Bagherzadeh , University of California at Irvine
pp. 148

Implementation of a Streaming Execution Unit (Abstract)

Dmitry Cheresiz , Leiden University
Harry A.G. Wijshoff , Leiden University
Stamatis Vassiliadis , Delft University of Technology
Ben Juurlink , Delft University of Technology
pp. 156
Verification and Test

Fault Latencies of Concurrent Checking FSMs (Abstract)

Sergei Ostanin , Tel Aviv University
Roman Goot , Academic Technological Institute
Ilya Levin , Tel Aviv University
pp. 174

Integrated Design and Test Generation Under Internet Based Environment MOSCITO (Abstract)

T. Hollstein , Technical University of Darmstadt
Z. Peng , Link?ping University
K.-H. Diener , Fraunhofer Institute for Integrated Circuits
A. Schneider , Fraunhofer Institute for Integrated Circuits
R. Ubar , Tallinn Technical University,
W. Kuzmicz , Warsaw University of Technology
E. Gramatova , Institute of Informatics
E. Ivask , Tallinn Technical University
pp. 187
Plenary — Keynote Session II

Networks on Silicon: Blessing or Nightmare? (Abstract)

Paul Wielage , Philips Research Laboratories
Kees Goossens , Philips Research Laboratories
pp. 196

Embedded Software: How To Make It Efficient? (Abstract)

Peter Marwedel , Universität Dortmund
pp. 201
Filter and Arithmetic Circuits

A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA (Abstract)

Hiroto Yasuura , Kyushu University
Takashi Yarnada , SANYO Electric Co., Ltd.
Yasoo Harada , SANYO Electric Co., Ltd.
Norihisa Takayarna , SANYO Electric Co., Ltd.
Shoji Goto , SANYO Electric Co., Ltd.
Yoshifurni Matsushita , SANYO Electric Co., Ltd.
pp. 210

Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor (Abstract)

D. Piso , Universidad Santiago de Compostela
J. D. Bruguera , Universidad Santiago de Compostela
J. A. Piñeiro , Universidad Santiago de Compostela
pp. 218
Circuit Synthesis and Optimisation

Decision Diagram Optimization Using Copy Properties (Abstract)

Dragan Janković , University of Niš
Radomir S. Stanković , University of Niš
Rolf Drechsler , University of Bremen
pp. 236

Use of the Autocorrelation Function in the Classification of Switching Functions (Abstract)

J. C. Muzio , University of Victoria
J. E. Rice , University of Victoria
pp. 244

Optimization of Equational Specifications Using Genetic Techniques (Abstract)

J. Lanchares , Universidad Complutense Madrid
A. Ibarra , Universidad Complutense Madrid
J. M. Mendías , Universidad Complutense Madrid
R. Hermida , Universidad Complutense Madrid
J. I. Hidalgo , Universidad Complutense Madrid
pp. 252

Synthesis of Multipurpose Reversible Logic Gates (Abstract)

Pawel Kerntopf , Warsaw University of Technology
pp. 259
Reconfigurable Computing Architectures

Improving mW/MHz Ratio in FPGAs Pipelined Designs (Abstract)

Graham Megson , University of Reading
Oswaldo Cadenas , University of Reading
pp. 276

Constant Coefficient Convolution Implemented in FPGAs (Abstract)

Kazimierz Wiatr , AGH Technical University of Cracow
Ernest Jamro , AGH Technical University of Cracow
pp. 291
High Level Synthesis

Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis (Abstract)

O. Peñalba , Universidad Complutense de Madrid
J. M. Mendías , Universidad Complutense de Madrid
M. C. Molina , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
pp. 308

An Efficient List-Based Scheduling Algorithm for High-Level Synthesis (Abstract)

Azeddien M. Sllame , Brno University of Technology
Vladimir Drabek , Brno University of Technology
pp. 316

Source Code Transformation to Improve Conditional Hardware Reuse (Abstract)

R. Hermida , Universidad Complutense de Madrid
0. Peñalba , Universidad Complutense de Madrid
J. M. Mendias , Universidad Complutense de Madrid
pp. 324
Poster Session

Reachability Analysis for Formal Verification of SystemC (Abstract)

Rolf Drechsler , University of Bremen
Daniel Große , Albert-Ludwigs-University
pp. 337

Simplifying Instruction Issue Logic in Superscalar Processors (Abstract)

Toshinori Sato , Kyushu Institute of Technology
Itsujiro Arita , Kyushu Institute of Technology
pp. 341

A Self-Timed Arithmetic Unit for Elliptic Curve Cryptography (Abstract)

Bernd Schnitzer , Graz University of Technology
Thomas Trathnigg , Graz University of Technology
Martin Feldhofer , Graz University of Technology
pp. 347

Low Power Strategy for a TFT Controller (Abstract)

Agatino Pennisi , STMicroelectronics
Giuseppe Notarangelo , STMicroelectronics
Marco Gibilaro , STMicroelectronics
Francesco Pappalardo , STMicroelectronics
Gaetano Palumbo , University of Catania
pp. 351

Hardware Implementation of a Memory Allocator (Abstract)

Jianwen Zhu , University of Toronto
Khushwinder Jasrotia , University of Toronto
pp. 355

Evolutionary Algorithm for State Assignment of Finite State Machines (Abstract)

Witold Kosiński , Polish-Japanese Institute of Information Technology
Mariusz Chyży , Polish-Japanese Institute of Information Technology
pp. 359
Specification and Modelling

Use of HDL Code Checkers to Support the IP Entrance Check — A Requirement Analysis (Abstract)

Ronny Frevert , FhG IIS, EAS Dresden
Steffen Rülke , FhG IIS, EAS Dresden
Torsten Schäfer , FhG IIS, EAS Dresden
Frank Dresig , AMD Saxony Manufacturing GmbH
pp. 364

On the Fundamental Design Gap in Terabit per Second Packet Switching (Abstract)

M. Verhappen , IBM Research, Zurich Research Laboratory
P. H. A. van der Putten , Eindhoven University of Technology
J. P. M. Voeten , Eindhoven University of Technology
pp. 371
Synthesis and Algorithms

Bit-Level Allocation of Multiple-Precision Specifications (Abstract)

J. M. Mendías , Universidad Complutense de Madrid
M. C. Molina , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
pp. 385
Author Index

Author Index (Abstract)

pp. 393
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