The Community for Technology Leaders
2013 Euromicro Conference on Digital System Design (2001)
Warsaw, Poland
Sept. 4, 2001 to Sept. 6, 2001
ISBN: 0-7695-1239-9
TABLE OF CONTENTS
System Design-Chair: Martyn Edwards

Header Compression in Handel-C -- An Internet Application and a New Design Language (Abstract)

Johan Ditmar , Ericsson Radio Systems AB, Sweden, Celoxica Ltd
Kjell Torkelsson , Ericsson Radio Systems AB, Sweden, Celoxica Ltd
pp. 0002

A Multi-Lingual Synthesis and Verification Environment (Abstract)

George Economakos , National Technical University of Athens
Vassilios Zoukos , INTRACOM S. A., Access and Transmission Department
Stergios Stergiou , National Technical University of Athens
George Papakonstantinou , National Technical University of Athens
pp. 0008

Application of Decision-Making Method for Architecture Selection of ADSL Modem (Abstract)

Tommi Salminen , VTT Electronics
Hannu Heusala , University of Oulu
Juha-Pekka Soininen , VTT Electronics
Sandrine Boumard , VTT Electronics
pp. 0021
Logic Synthesis-Chair: Tadeusz Luba

Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures (Abstract)

L. Jozwiak , Eindhoven University of Technology
A. Chojnacki , Eindhoven University of Technology
pp. 0030

Practical Aspects of Logic Synthesis Based on Functional Decomposition (Abstract)

Zbigniew Jachna , Military Academy of Technology
Ireneusz Brzozowski , University of Mining and Metallurgy AGH, Institute of Electronics
Mariusz Rawski , Warsaw University of Technology, Institute of Telecommunications
Rafal Rzechowski , Warsaw University of Technology, Institute of Telecommunications
pp. 0038

Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis (Abstract)

L. Józwiak , Eindhoven University of Technology
A. Slusarczyk , Eindhoven University of Technology
A. Chojnacki , Eindhoven University of Technology
pp. 0046

Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement (Abstract)

W. Günther , Siemens AG
T. Eschbach , Institute of Computer Science, Albert-Ludwigs-University Corporate Technology
B. Becker , Institute of Computer Science, Albert-Ludwigs-University Corporate Technology
R. Drechsler , Siemens AG
pp. 0054
Embedded Systems-Chair: Krzysztof Kuchcinski

Hierarchical Modeling and Verification of Embedded Systems (Abstract)

Luis Alejandro Cortés , Link?ping University
Petru Eles , Link?ping University
Zebo Peng , Link?ping University
pp. 0063
Decision Diagrams and Synthesis-Chair: Marek Perkowski

Minimization of OPKFDDs Using Genetic Algorithms (Abstract)

M. Jung , Chonnam National University
G. Lee , Chonnam National University
R. Drechsler , Siemens, AG
S. Park , Hanyang University
pp. 0072

An Approach to Minimization of Decision Diagrams (Abstract)

Pawel Kerntopf , Warsaw University of Technology
pp. 0079

Synthesis of ASM-based Self-Checking Controllers (Abstract)

Ilya Levin , Tel-Aviv University
Vladimir Sinelnikov , Academic Technological Institute
Mark Karpovsky , Boston University
pp. 0087

Two-Criterial Constraint-Driven FSM State Encoding for Low Power (Abstract)

Maria José Avedillo , Instituto de Microelectr?nica de Sevilla
Günter Franke , Hochschule f?r Technik und Wirtschaft
Steffen Rülke , Fraunhofer-Institut f?r Integrierte Schaltungen
Manfred Koegst , Fraunhofer-Institut f?r Integrierte Schaltungen
pp. 0094
Reconfigurable Computing-Chair: Adam Postula
Reconfigurable Computing-Chair: Rolf Ernst

Optimisation of PPMC Model for Hardware Implementation (Abstract)

C.Feregrino Uribe , Loughborough University
S.R. Jones , Loughborough University
pp. 0120

A Run-Time Support Environment for Reconfigurable Systems (Abstract)

L. Bubb , UMIST
C. Pimlott , UMIST
M. Edwards , UMIST
M. Vakondios , UMIST
K. Rees , UMIST
J. Yates , UMIST
M. Stewart , UMIST
P. Green , UMIST
A. Taylor , UMIST
pp. 0135
Synthesis and Verification Posters-Chair: Rolf Drechsler

Level Assignment for Displaying Combinational Logic (Abstract)

Gerhard Angst , Siemens AG Concept Engineering GmbH
Lothar Linhard , Siemens AG Concept Engineering GmbH
Rolf Drechsler , Siemens AG Concept Engineering GmbH
Wolfgang Günther , Siemens AG Concept Engineering GmbH
pp. 0148

System Modeling in the COSMA Environment (Abstract)

W. B. Daszczuk , Warsaw University of Technology
J. Miescicki , Warsaw University of Technology
W. Grabski , Warsaw University of Technology
J. Wytrebowicz , Warsaw University of Technology
pp. 0152

Applying Formal Verification with Protocol Compiler (Abstract)

Ulrich Holtmann , Synopsys GmbH
Christian Stangier , University of Trier
pp. 0165
Processor Design-Chair: Antonio Nunez

Dynamic Branch Prediction Using Neural Networks (Abstract)

Gordon Steven , University of Hertfordshire
Fleur Steven , University of Hertfordshire
Lucian Vintan , University "Lucian Blaga" of Sibiu
Rubén Anguera , University of Hertfordshire
Colin Egan , University of Hertfordshire
pp. 0178

Applying Caching to Two-Level Adaptive Branch Prediction (Abstract)

Colin Egan , University of Hertfordshire
Gordon B. Steven , University of Hertfordshire
Lucian Vintan , University of Sibiu
Won Shim , Seoul National University of Technology
pp. 0186

Experimental Evaluation of CPU Performance Features (Abstract)

J. Sosnowski , Warsaw University of Technology
J. Nowicki , Warsaw University of Technology
R. Jurkiewicz , Warsaw University of Technology
pp. 0194

A Comparison of Five Different Multiprocessor SoC Bus Architectures (Abstract)

Vincent J. Mooney , Georgia Institute of Technology
Kyeong Keol Ryu , Georgia Institute of Technology
Eung Shin , Georgia Institute of Technology
pp. 0202
Synthesis and Test-Chair: Andrzej Krasniewski

A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines (Abstract)

Reinhold Weiss , Technical University Graz
Christian Steger , Technical University Graz
Egon Teiniker , Technical University Graz
Christian Kreiner , Technical University Graz
pp. 0212

Self-Testing of User-Programmed FPGAs Based on the Concept of Linear Segments (Abstract)

Mariusz Rawski , Warsaw University of Technology
Pawel Tomaszewicz , Warsaw University of Technology
pp. 0236
Reversible Logic-Chair: Lech J?zwiak

Regular Realization of Symmetric Functions Using Reversible Logic (Abstract)

Bart Massey , Portland State University
Xiaoyu Song , Portland State University
Pawel Kerntopf , Technical University of Warsaw
Malgorzata Chrzanowska-Jeske , Portland State University
Marek Perkowski , Portland State University
Alan Mishchenko , Portland State University
Lech Jozwiak , Technical University of Eindhoven
Alan Coppola , Cypress Semiconductor Northwest
Anas Al-Rabadi , Portland State University
pp. 0245
Specialised Architectures-Chair: Steve Guccione

FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation (Abstract)

J.D. Bruguera , University Santiago de Compostela
J.A. Piñeiro , University Santiago de Compostela
pp. 0262

Cork Stopper Classification Using FPGAs and Digital Image Processing Techniques (Abstract)

Miguel A. Vega-Rodríguez , University de Extremadura
Juan A. Gómez-Pulido , University de Extremadura
Juan M. Sánchez-Pérez , University de Extremadura
pp. 0270

Pipelining Considerations for an FPGA Case (Abstract)

Graham Megson , University of Reading
Oswaldo Cadenas , University of Reading
pp. 0276
Synthesis-Chair: Adam Pawlak

On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization (Abstract)

Luis Entrena , University Carlos III of Madrid
Enrique San Millán , University Carlos III of Madrid
José Alberto Espejo , University Carlos III of Madrid
pp. 0292

On the Use of Mutations in Boolean Minimization (Abstract)

Jan Hlavicka , Czech Technical University
Petr Fiser , Czech Technical University
pp. 0300
Test and Design for Testability-Chair: Raimond Ubar

Fast Test Cost Calculation for Hybrid BIST in Digital Systems (Abstract)

Zebo Peng , Link?ping University
Elmet Orasson , Tallinn Technical University
Raimund Ubar , Tallinn Technical University
Rein Raidma , Tallinn Technical University
Gert Jervan , Link?ping University
pp. 0318

Test Strategies on Functionally Partitioned Module-Based Programmable Architecture for Base-Band Processing (Abstract)

Adam Postula , The University of Queensland
Simon Leung , The University of Queensland
Ahmed Hemani , Spirea AB, Kista Science Park, Electrum 229
pp. 0326
Processor Design-Chair: Janusz Sosnowski

High-Performance Floating Point Divide (Abstract)

Michael J. Flynn , Stanford University
Albert A. Liddicoat , Stanford University
pp. 0354
Specialised Architectures Posters-Chair: Kjell Torkelsson

An Assesment of FPGA Suitability for Implementation of Real-Time Motion Estimation (Abstract)

Kazimierz Wiatr , AGH Technical University of Cracow
Andrzej Ryszko , AGH Technical University of Cracow
pp. 0364

Portable Acquisition System for Measurements of Pressures, Temperatures and Humidity in Lower Limb Prosthesis (Abstract)

G. Coldani , Universit? di Pavia
R. Lombardi , Universit? di Pavia
G. Danese , Universit? di Pavia
P. Ghidetti , Universit? di Pavia
F. Leporati , Universit? di Pavia
R. Gandolfi , Universit? di Pavia
pp. 0368

A MIMD-Based Multi Threaded Real-Time Processor for Pattern Recognition (Abstract)

M.W. Schulz , Ruprecht-Karls-University
R. Schneider , Ruprecht-Karls-University
C. Reichling , Ruprecht-Karls-University
V. Lindenstruth , Ruprecht-Karls-University
J. de Cuveland , Ruprecht-Karls-University
F. Lesser , Ruprecht-Karls-University
pp. 0372

Synchronizing a High-Speed SIMD Processor Array (Abstract)

Lars Bengtsson , Chalmers University of Technology
Stefan Lund , Halmstad University
pp. 0376

Pipelined Genetic Architecture with Fitness on the Fly (Abstract)

A. Ibarra , Universidad Complutense Madrid
F. Saenz , Universidad Complutense Madrid
J.I. Hidalgo , Universidad Complutense Madrid
J. Lanchares , Universidad Complutense Madrid
pp. 0382

A Wireless Interconnection Network for Parallel Processing (Abstract)

Daniel Tabak , George Mason University
Jacek Marczynski , George Mason University
pp. 0386

Improving Single-Thread Fetch Performance on a Multithreaded Processor (Abstract)

J.C. Moure , Universidad Aut?noma de Barcelona
E. Luque , Universidad Aut?noma de Barcelona
R.B. García , Universidad Aut?noma de Barcelona
D.I. Rexachs , Universidad Aut?noma de Barcelona
pp. 0390

Adaptability, Extensibility, and Flexibility in Real-Time Operating Systems (Abstract)

Vincent J. Mooney , Georgia Institute of Technology
Pramote Kuacharoen , Georgia Institute of Technology
Vijay K. Madisetti , Georgia Institute of Technology
Tankut Akgul , Georgia Institute of Technology
pp. 0400
Physical Design-Chair: Agnieszka Konczykowska

Timing Driven Wiring on an Advanced Microprocessor (Abstract)

Stephen Geissler , IBM Microelectronics Division
Paul Kartschoke , IBM Microelectronics Division
pp. 0408

Interconnect-Driven Short-Circuit Power Modeling (Abstract)

Daniel Eckerbert , Link?pings Universitet
Per Larsson-Edefors , Link?pings Universitet
pp. 0414

A Global Routing Technique for Wave-Steering Design Methodology (Abstract)

Arindam Mukherjee , University of California, Santa Barbara
Amit Singh , University of California, Santa Barbara
Nobuo Funabiki , Okayama University
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 0430
Specialised Architectures-Chair: Daniel Tabak

Synchronizing Low-Cost Energy Aware Sensors in a Short-range Wireless Cell (Abstract)

Olavi Vähämäki , ABB Corporate Research Oy
Mikael M. Nordman , Helsinki University of Technology
pp. 0438

A Multiple Context Reconfigurable Functional Unit (Abstract)

Daniel Tabak , George Mason University
Michael C. Miller , George Mason University
pp. 0446

FPGA Based Controller for Heterogeneous Image Processing System (Abstract)

Jaromir Przybylo , University of Mining and Metallurgy
Marek Gorgon , University of Mining and Metallurgy
pp. 0453

FPGA Implementation of Addition as a Part of the Convolution (Abstract)

Ernest Jamro , AGH Technical University
Kazimierz Wiatr , AGH Technical University
pp. 0458

Genetic Programming in FPGA Implementation of Addition as a Part of the Convolution (Abstract)

Ernest Jamro , AGH Technical University of Cracow
Kazimierz Wiatr , AGH Technical University of Cracow
pp. 0466

Author Index (PDF)

pp. 0475
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