Scheduling policies for fault tolerance in a VLSI processor (PDF)
A CMOS fault tolerant architecture for switch-level faults (PDF)
A defect and fault tolerant interconnection network strategy for WASP devices (PDF)
Implementation of a gracefully degradable binary tree in programmable multi-chip modules (PDF)
Fault-tolerant modular convolvers (PDF)
Augmenting scan path SRLs with an XOR network to enhance delay fault testing (PDF)
On the testability of CMOS feedback amplifiers (PDF)
Efficient critical area algorithms and their application to yield improvement and test strategies (PDF)
The effect of wire length minimization on yield (PDF)
Laser processes for defect correction in large area VLSI systems (PDF)
Synthesis of multi-level self-checking logic (PDF)
Design of cover circuits for monitoring the output of a MISA (PDF)
CMOS self checking circuits with faulty sequential functional blocks (PDF)
Highly testable and compact 1-out-of-n CMOS checkers (PDF)
Some results on improving the code length of SbEC-DED codes (PDF)
Reliability estimation for time redundant error correcting adders and multipliers (PDF)
A fault-tolerant associative approach to on-line memory repair (PDF)
Fault tolerant design using error correcting code for multilayer neural networks (PDF)
Defect and fault tolerant scan chains (PDF)
Reconfiguration in 3D meshes (PDF)
On soft switch programming for reconfigurable array systems (PDF)
A self-reconfiguration architecture for mesh arrays (PDF)
A general method to design and reconfigure loop-based linear arrays (PDF)
Statistical analysis of particle/defect data experiments using Poisson and logistic regression (PDF)
A yield study of VLSI adders (PDF)
Yield enhancement with particle defects reduction (PDF)
On the analysis of routing, cells and adjacency faults in CMOS digital circuits (PDF)
Alternative approaches to fault detection in FSMs (PDF)
Using Fourier analyses to enhance IC testability (PDF)
Multi-layer interconnect yield model for mega bit BiCMOS SRAMs (PDF)
Index of authors (PDF)
