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IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (1994)
Montreal, Quebec, Canada
Oct. 17, 1994 to Oct. 19, 1994
ISSN: 1550-5774
ISBN: 0-8186-6307-3
TABLE OF CONTENTS

Scheduling policies for fault tolerance in a VLSI processor (PDF)

Y.-N. Shen , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 1-9

A defect and fault tolerant interconnection network strategy for WASP devices (PDF)

M.B.A. Hussaini , Dept. of Electr. Eng. & Electron., Brunel Univ., Uxbridge, UK
pp. 19-27

Implementation of a gracefully degradable binary tree in programmable multi-chip modules (PDF)

S. Goldberg , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 28-36

Fault-tolerant modular convolvers (PDF)

L. Dadda , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
pp. 37-45

Augmenting scan path SRLs with an XOR network to enhance delay fault testing (PDF)

Zaifu Zhang , Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
pp. 55-63

On the testability of CMOS feedback amplifiers (PDF)

A.J. Bishop , Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
pp. 65-73

Roundoff error-free tests in algorithm-based fault tolerant matrix operations on 2-D processor arrays (PDF)

D.-Y.D. Wei , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 74-82

The effect of wire length minimization on yield (PDF)

V.K.R. Chiluvuri , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 97-105

Laser processes for defect correction in large area VLSI systems (PDF)

G.H. Chapman , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 106-114

Synthesis of multi-level self-checking logic (PDF)

F. Salice , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
pp. 115-123

Design of cover circuits for monitoring the output of a MISA (PDF)

T. Bogue , Dept. of Comput. Sci., Univ. of Western Ontario, London, Ont., Canada
pp. 124-132

CMOS self checking circuits with faulty sequential functional blocks (PDF)

C. Metra , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
pp. 133-141

Highly testable and compact 1-out-of-n CMOS checkers (PDF)

C. Metra , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
pp. 142-150

Some results on improving the code length of SbEC-DED codes (PDF)

Sihai Xiao , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 151-158

Reliability estimation for time redundant error correcting adders and multipliers (PDF)

Yuang-Ming Hsu , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 159-167

A fault-tolerant associative approach to on-line memory repair (PDF)

Jien-Chung Lo , Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA
pp. 168-176

Fault tolerant design using error correcting code for multilayer neural networks (PDF)

H. Ito , Dept. of Inf. & Comput. Sci., Chiba Univ., Japan
pp. 177-184

Defect and fault tolerant scan chains (PDF)

R. Kermouche , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
pp. 185-193

Reconfiguration in 3D meshes (PDF)

Anuj Chandra , Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
pp. 194-202

On soft switch programming for reconfigurable array systems (PDF)

T. Liu , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 203-211

A self-reconfiguration architecture for mesh arrays (PDF)

S. Horiguchi , Graduate Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
pp. 212-220

A general method to design and reconfigure loop-based linear arrays (PDF)

Weiping Shi , Dept. of Comput. Sci., Univ. of North Texas, Denton, TX, USA
pp. 221-229

A yield study of VLSI adders (PDF)

Zhan Chen , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 239-245

Yield enhancement with particle defects reduction (PDF)

K. Mori , Sony Microelectron., San Antonio, TX, USA
pp. 246-253

Alternative approaches to fault detection in FSMs (PDF)

R. Leveugle , Inst. Nat. Polytech. de Grenoble, France
pp. 271-279

Using Fourier analyses to enhance IC testability (PDF)

C. Thibeault , Dept. of Electr. Eng., Ecole de Technol. Superieure, Montreal, Que., Canada
pp. 280-288

Multi-layer interconnect yield model for mega bit BiCMOS SRAMs (PDF)

V.N. Rayapati , Succ. Centre-Ville, Montreal, Que., Canada
pp. 289-297

Index of authors (PDF)

pp. 299
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