The Community for Technology Leaders
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (1993)
Venice, Italy
Oct. 27, 1993 to Oct. 29, 1993
ISSN: 1550-5774
ISBN: 0-8186-3502-9

Analysis and comparison of fault tolerant FSM architecture based on SEC codes (PDF)

R. Rochet , Inst. Nat. Polytech. de Grenoble/CSI, Grenoble, France
pp. 9-16

Block implementation of fault-tolerant LMS adaptive FIR filters (PDF)

L. Lin , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
pp. 17-24

Fault-tolerant sorting using VLSI processor arrays (PDF)

H.Y. Youn , Dept. of Comput. Sci. Eng., Texas Univ., Arlington, TX, USA
pp. 25-32

Detection of defective media in disks (PDF)

H.H. Kari , Dept. of Comput. Sci, Helsinki Univ. of Technol., Espoo, Finland
pp. 49-55

A two-phase reconfiguration strategy for extracting linear arrays out of two-dimensional architectures (PDF)

H. Al-Asaad , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
pp. 56-63

On the configuration of degradable VLSI/WSI arrays (PDF)

C.P. Low , Dept. of Inf. Syst. & Comput. Sci., Nat. Univ. of Singapore, Singapore
pp. 64-71

A defect-tolerant design for WSI interconnection networks and its application to hypercube (PDF)

H. Ito , Dept. of Inf. & Comput. Sci., Ciuba Univ., Japan
pp. 80-87

On the reconfigurable operation of arrays with defects for image processing (PDF)

J. Salinas , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 88-95

Front-end electronics in the radiation environment of LHC (PDF)

A. Kerek , Manne Siegbahn Inst. of Phys., Stockholm
pp. 96-100

Analysis of the floating gate defect in CMOS (PDF)

V.H. Champac , Dept. d'Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 101-108

Fast multi-layer critical area computation (PDF)

H. Xue , Dept. of EE, Eindhoven Univ. of Technol., Netherlands
pp. 117-124

A logistic regression yield model for SRAM bit fail patterns (PDF)

R.S. Collica , Digital Equipment Corp., MA, USA
pp. 127-135

Yield model for ASIC and processor chips (PDF)

C.H. Stapper , IBM Technology Products, Essex Junction, VT, USA
pp. 136-143

Some results on yield and local design rule relaxation (PDF)

J. Crepeau , Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
pp. 144-151

Does the floorplan of a chip affect its yield? (PDF)

Z. Koren , Massachusetts Univ., Amherst, MA, USA
pp. 159-166

An interactive yield estimator as a VLSI CAD tool (PDF)

I.A. Wagner , IBM Israel - Sci. & Technol., Haifa, Israel
pp. 167-174

Topological optimization of PLAs for yield enhancement (PDF)

V.K.R. Chiluvuri , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 175-182

Fault detection in sequential circuits through functional testing (PDF)

G. Buonanno , Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy
pp. 191-198

Current testing viability in dynamic CMOS circuits (PDF)

M. Renovell , LIRMM, Univ. de Montpellier II, France
pp. 207-214

Probabilistic identification of critical components for circuit delays (PDF)

D. Wessels , VLSI Design & Test Group, Victoria Univ., BC, Canada
pp. 215-222

Design and implementation of a merged on-line and off-line self-testable architecture (PDF)

X. Sun , Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
pp. 247-254

Complete tests in algorithm-based fault-tolerant matrix operation on processor arrays (PDF)

D.-Y.D. Wei , Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
pp. 255-262

A probabilistic measurement for totally self-checking circuits (PDF)

J.-C. Lo , Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA
pp. 263-270

VLSI concurrent error correcting adders and multipliers (PDF)

Y.-M. Hsu , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 287-294

Functional testing of linear circuits using transient response analysis (PDF)

D. Taylor , Div. of Electron. & Commun., Huddersfield Univ., UK
pp. 295-302

Neural networks for multiple fault diagnosis in analog circuits (PDF)

A. Fanni , Istituto di Elettrotecnica, Cagliari Univ., Italy
pp. 303-310

Catastrophic defects oriented testability analysis of a class AB amplifier (PDF)

M. Sachdev , Philips Res. Lab., Eindhoven, Netherlands
pp. 319-326

Device mismatch limitations on performance of a Hamming distance classifier (PDF)

N. Kumar , Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
pp. 327-334

Author index (PDF)

pp. 335-336
85 ms
(Ver 3.3 (11022016))