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Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (1992)
Dallas, TX, USA
Nov. 4, 1992 to Nov. 6, 1992
ISSN: 1550-5774
ISBN: 0-8186-2837-5
TABLE OF CONTENTS

New routing and compaction strategies for yield enhancement (PDF)

V.K.R. Chiluvuri , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 325-334

Improved layer assignment for packaging multichip modules (PDF)

C.-H. Chen , Dept. of Comput. Sci., Texas Univ., Dallas, Richardson, TX, USA
M.H. Heydari , Dept. of Comput. Sci., Texas Univ., Dallas, Richardson, TX, USA
I.G. Tollis , Dept. of Comput. Sci., Texas Univ., Dallas, Richardson, TX, USA
C. Xia , Dept. of Comput. Sci., Texas Univ., Dallas, Richardson, TX, USA
pp. 315-324

A universal self-test design for chip, card and system (PDF)

D.M. Wu , Adv. Workstation Div., IBM, Austin, TX, USA
pp. 305-314

Practical application of automated fault diagnosis at the chip and board levels (PDF)

M. Maccanelli , Texas Instruments, Dallas, TX, USA
A. Halliday , Texas Instruments, Dallas, TX, USA
B. Bell , Texas Instruments, Dallas, TX, USA
D. Steiss , Texas Instruments, Dallas, TX, USA
K.M. Butler , Texas Instruments, Dallas, TX, USA
pp. 297-304

High-speed parallel input-output bit-sliced fault-tolerant convolvers (PDF)

L. Dadda , Dipartimento di Elettronica, Politecnico di Milano, Italy
M. Sami , Dipartimento di Elettronica, Politecnico di Milano, Italy
pp. 287-296

A fast pipelined complex multiplier: the fault tolerance issues (PDF)

L. Breveglieri , Dipartimento di Elettronica, Politecnico di Milano, Italy
V. Piuri , Dipartimento di Elettronica, Politecnico di Milano, Italy
D. Sciuto , Dipartimento di Elettronica, Politecnico di Milano, Italy
pp. 277-286

Analysis of defect maps of large area VLSI ICs (PDF)

I. Koren , Massachusetts Univ., Amherst, MA, USA
Z. Koren , Massachusetts Univ., Amherst, MA, USA
pp. 267-276

Time redundant error correcting adders and multipliers (PDF)

Y.M. Hsu , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 247-256

An efficient algorithm-based fault tolerance design using extended rearranged Hamming checksum (PDF)

C.G. Oh , Dept. of Comput. Sci. Eng., Texas Univ., Arlington, TX, USA
H.Y. Youn , Dept. of Comput. Sci. Eng., Texas Univ., Arlington, TX, USA
V.K. Raj , Dept. of Comput. Sci. Eng., Texas Univ., Arlington, TX, USA
pp. 237-246

A WSI hypercube design using shift channels (PDF)

H. Ito , Dept. of Inf. & Comput. Sci., Chiba Univ., Japan
E. Hosoya , Dept. of Inf. & Comput. Sci., Chiba Univ., Japan
pp. 227-236

Design rule centring for row redundant content addressable memories (PDF)

W.B. Noghani , Dept. of Electr. Eng., Brunel Univ., Uxbridge, UK
I.P. Jalowiecki , Dept. of Electr. Eng., Brunel Univ., Uxbridge, UK
pp. 217-226

Tolerance of delay faults (PDF)

D.M.H. Walker , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 207-216

Modeling of 3-dimensional defects in integrated circuits (PDF)

J.P. de Gyvez , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
S.M. Dani , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 197-206

Spatial fault simulation and the saturation effect (PDF)

C.H. Stapper , IBM Technology Products, Essex Junction, VT, USA
pp. 187-196

Nondeterministic adaptive routing techniques for WSI processor arrays (PDF)

D.C. Blight , Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
R.D. McLeod , Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
pp. 177-186

On fault probabilities and yield models for analog VLSI neural networks (PDF)

P.M. Furth , Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
A.G. Andreou , Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
pp. 167-176

Defect level estimation for digital ICs (PDF)

J.J.T. Sousa , INESC, IST, CEAUTL, Lisboa, Portugal
J.P. Teixeira , INESC, IST, CEAUTL, Lisboa, Portugal
pp. 32-41

Defect density assessment in an integrated circuit fabrication line (PDF)

R.E. Harris , Div. of Digital Int., Digital Commun., Newport Beach, CA, USA
pp. 2-11

Comparing results from defect-tolerant yield models (PDF)

C. Thibeault , Dept. of Math. & Comput. Sci., Quebec Univ., Montreal, Que., Canada
pp. 22-31

Efficient bi-level reconfiguration algorithms for fault tolerant arrays (PDF)

R. Libeskind-Hadas , Dept. of Comput. Sci., Illinois Univ., Urbana-Champaign, IL, USA
pp. 42-51

A real-time reconfiguration algorithm for fault-tolerant VLSI and WSI arrays (PDF)

H. Al-Asaad , Dept. of Electr. & Comput. Eng., Northeastern Univ., MA, USA
M. Vai , Dept. of Electr. & Comput. Eng., Northeastern Univ., MA, USA
pp. 52-59

Fault spectrum analysis for fast spare allocation in reconfigurable arrays (PDF)

W. Che , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 60-69

Recognition of catastrophic faults (PDF)

A. Nayak , Center for Parallel & Distributed Comput., Sch. of Comput. Sci., Carleton Univ., Ottawa, Ont., Canada
pp. 70-79

Bridging faults modeling and detection in CMOS combinational gates (PDF)

G. Buonanno , Dipartimento di Elettronica, Politecnico di Milano, Italy
pp. 80-89

Scan-based testability for fault-tolerant architectures (PDF)

A. DeHon , AI Lab., MIT, Cambridge, MA, USA
pp. 90-99

Time complexity of systolic array testing (PDF)

N. Faroughi , Dept. of Comput. Sci., California State Univ., Sacramento, CA, USA
pp. 100-108

Concurrent error detection in ALUs by recomputing with rotated operands (PDF)

J. Li , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 109-116

PLA decomposition to reduce the cost of concurrent checking (PDF)

D. Wessels , Victoria Univ., BC, Canada
J.C. Muzio , Victoria Univ., BC, Canada
pp. 117-126

Arithmetic codes for concurrent error detection in artificial neural networks: the case of AN+B codes (PDF)

V. Piuri , Dept. of Electron., Politecnico di Milano, Italy
M. Sami , Dept. of Electron., Politecnico di Milano, Italy
R. Stefanelli , Dept. of Electron., Politecnico di Milano, Italy
pp. 127-136

Lessons learnt from designing a wafer scale 2D array (PDF)

A. Boubekeur , Inst. Nat. Polytech. de Grenoble, France
J.L. Patry , Inst. Nat. Polytech. de Grenoble, France
G. Saucier , Inst. Nat. Polytech. de Grenoble, France
M. Slimane-kadi , Inst. Nat. Polytech. de Grenoble, France
pp. 137-146

Probabilistic diagnosis in wafer-scale systems (PDF)

A.K. Somani , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
J. Wang , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 147-156

Probabilistic analysis of memory reconfiguration in the presence of coupling faults (PDF)

C.P. Low , Dept. of Inf. Syst. & Comput. Sci., Nat. Univ. of Singapore, Singapore
H.W. Leong , Dept. of Inf. Syst. & Comput. Sci., Nat. Univ. of Singapore, Singapore
pp. 157-166
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