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1991 International Workshop on Defect and Fault Tolerance on VLSI Systems (1991)
Hidden Valley, Pennsylvania, USA
Nov. 18, 1991 to Nov. 20, 1991
ISSN: 1550-5774
ISBN: 0-8186-2457-4
TABLE OF CONTENTS

Optimization of parametric yield (PDF)

S.W. Director , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 1-18

Defect tolerance and yield for a WSI rapid prototyping architecture (PDF)

V.K. Jain , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
D.C. Keezer , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
H. Hikawa , Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
pp. 24-27

Current-mode techniques for analog VLSI: technology and defect tolerance issues (PDF)

A.G. Andreou , Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
pp. 28-31

Circuit design for a large area high-performance crossbar switch (PDF)

M. Patyra , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 32-45

Improved yield models for fault-tolerant random-access memory chips (PDF)

C.H. Stapper , IBM Gen. Technol. Div., Essex Junction, VT, USA
pp. 46-59

Applications of a mechanistic yield model for MOSIC chips (PDF)

C.M. Drum , AT&T Bell Labs., Allentown, PA, USA
pp. 60-62

Circuit-level modeling of spot defects (PDF)

D. Gaitonde , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D.M.H. Walker , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 63-66

A model for enhanced manufacturability of defect tolerant integrated circuits (PDF)

Z. Koren , Massachusetts Univ., Amherst, MA, USA
I. Koren , Massachusetts Univ., Amherst, MA, USA
pp. 81-92

Harvest rate of reconfigurable pipelines (PDF)

Weiping Shi , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Ming-Feng Chang , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W. Kent Fuchs , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 93-102

Neural networks on silicon: the mapping of hardware faults onto behavioral errors (PDF)

V. Piuri , Dipartimento di Elettronica, Politecnico di Milano, Italy
M. Sami , Dipartimento di Elettronica, Politecnico di Milano, Italy
R. Stefanelli , Dipartimento di Elettronica, Politecnico di Milano, Italy
pp. 103-115

Key issues in the design of a fault-tolerant core avionics computer based on the mesh architecture (PDF)

A.W. Nordsieck , Boeing High Technol. Center, Seattle, WA, USA
W.M. Yost , Boeing High Technol. Center, Seattle, WA, USA
C.A. Young , Boeing High Technol. Center, Seattle, WA, USA
pp. 120-123

Overview of fault handling for the chaos router (PDF)

K. Bolding , Washington Univ., Seattle, WA, USA
L. Snyder , Washington Univ., Seattle, WA, USA
pp. 124-127

Effects of fault tolerance on the reliability of memory array supports (PDF)

F.J. Aichelmann , IBM Gen. Technol. Div., Hopewell Junction, NY, USA
pp. 128-138

Concurrent error diagnosis in mesh array architectures based on overlapping H-processes (PDF)

E.S. Manolakos , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
D. Dakhil , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
M. Vai , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
pp. 139-152

Reliability evaluation of FUSS and other reconfiguration schemes (PDF)

N. Lopez-Benitez , Dept. of Electr. Eng., Louisiana Tech. Univ., Ruston, LA, USA
pp. 153-156

A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy (PDF)

Yung-Yuan Chen , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
S.J. Upadhyaya , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 157-160

On the modeling and testing of gate oxide shorts in CMOS logic gates (PDF)

Hong Hao , Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey , Center for Reliable Comput., Stanford Univ., CA, USA
pp. 161-174

On the testability of realistic bridging faults (PDF)

M.B. Santos , INESC, IST, Lisboa, Portugal
J.J.T. Sousa , INESC, IST, Lisboa, Portugal
F.M. Goncalves , INESC, IST, Lisboa, Portugal
J.P. Teixeira , INESC, IST, Lisboa, Portugal
pp. 175-178

A bottom-up methodology to characterize delay faults (PDF)

J. Zubairi , Syracuse Univ., NY, USA
G.L. Craig , Syracuse Univ., NY, USA
pp. 183-186

Delay fault simulation of self-checking error checkers (PDF)

K. Hirabayashi , ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
pp. 187-190

Almost sure diagnosis of almost every good element (PDF)

L. LaForge , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
Kaiyuan Huang , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
V.K. Agarwal , Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
pp. 191-194

A method for the consistent reporting of fault coverage (PDF)

W.H. Debany , Rome Lab., RL/ERDA, Griffiss AFB, NY, USA
K.A. Kwait , Rome Lab., RL/ERDA, Griffiss AFB, NY, USA
pp. 195-198

Concurrent built-in self-test with reduced fault latency (PDF)

Y.-N. Shen , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 199-212

Array architecture for ATG with 100% fault coverage (PDF)

K. El-Ayat , Actel Corp., Sunnyvale, CA, USA
R. Cahn , Actel Corp., Sunnyvale, CA, USA
Chung Lau Chan , Actel Corp., Sunnyvale, CA, USA
T. Speers , Actel Corp., Sunnyvale, CA, USA
pp. 213-226

Physical boundaries of performance: the interconnection perspective (PDF)

S.K. Tewksbury , Dept. of Electr. & Comput. Eng., West Virginia Univ., Morgantown, WV, USA
pp. 227-246

Efficient and optimal fault-to-spare assignments in doubly fault tolerant arrays (PDF)

N. Shrivastava , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
R. Melhem , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
pp. 247-259

Fast search algorithms for reconfiguration problems (PDF)

R. Libeskind-Hadas , Dept. of Comput. Sci., Illinois Univ., Urbana-Champaign, IL, USA
C.L. Liu , Dept. of Comput. Sci., Illinois Univ., Urbana-Champaign, IL, USA
pp. 260-273

Reconfiguration of time-multiplexed binary trees for satellite communication (PDF)

K. Raghunandan , Centre for Satellite Eng. Res., Surrey Univ., Guildford, UK
F.P. Coakley , Centre for Satellite Eng. Res., Surrey Univ., Guildford, UK
pp. 274-287

Hex-repair: a new approach to hexagonal array reconfiguration (PDF)

R. Venkateswaran , Michigan Univ., Ann Arbor, MI, USA
P. Mazumder , Michigan Univ., Ann Arbor, MI, USA
Kang G. Shin , Michigan Univ., Ann Arbor, MI, USA
pp. 288-291

Some results and open problems concerning memory reconfiguration under clustered fault models (PDF)

D.M. Blough , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 292-295

State-of-the-art of the wafer scale ELSA project (PDF)

A. Boubekeur , INPG/CSI, Grenoble, France
J.-I. Patry , INPG/CSI, Grenoble, France
G. Saucier , INPG/CSI, Grenoble, France
pp. 296-299
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