The Community for Technology Leaders
2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) (2013)
New York City, NY, USA
Oct. 2, 2013 to Oct. 4, 2013
ISSN: 1550-5774
ISBN: 978-1-4799-1583-5
TABLE OF CONTENTS

Title pages (Abstract)

pp. 1-14

Classes of difficult-to-diagnose transition fault clusters (Abstract)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
pp. 1-6

Mixed structural-functional path delay test generation and compaction (Abstract)

Kun Bian , Texas A&M University, College Station, 77843, USA
D. M. H. Walker , Texas A&M University, College Station, 77843, USA
Sunil P. Khatri , Texas A&M University, College Station, 77843, USA
Shayak Lahiri , Microsoft, Redmond, WA 98052, USA
pp. 7-12

A data mining approach to incremental adaptive functional diagnosis (Abstract)

Cristiana Bolchini , Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria, Italy
Elisa Quintarelli , Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria, Italy
Fabio Salice , Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria, Italy
Paolo Garza , Politecnico di Torino, Dip. Automatica e Informatica, Italy
pp. 13-18

An energy-efficient and robust millimeter-wave Wireless Network-on-Chip architecture (Abstract)

Naseef Mansoor , Rochester Institute of Technology, NY, USA
Amlan Ganguly , Rochester Institute of Technology, NY, USA
Manoj Prashanth Yuvaraj , Rochester Institute of Technology, NY, USA
pp. 19-24

CFEDR: Control-flow error detection and recovery using encoded signatures monitoring (Abstract)

Lanfang Tan , School of Computer, National University of Defense Technology, Changsha, China
Ying Tan , School of Computer, Sichuan University, Chengdu, China
Jianjun Xu , School of Computer, National University of Defense Technology, Changsha, China
pp. 25-32

A low power architecture for online detection of execution errors in SMT processors (Abstract)

Rance Rodrigues , Dept. of Electr. & Comput. Eng., Univ. of Massachusetts Amherst, Amherst, MA, USA
Sandip Kundu , Dept. of Electr. & Comput. Eng., Univ. of Massachusetts Amherst, Amherst, MA, USA
pp. 33-38

SAT-based code synthesis for fault-secure circuits (Abstract)

Atefe Dalirsani , ITI, Universität Stuttgart, Pfaffenwaldring 47, D-70569, Germany
Michael A. Kochte , ITI, Universität Stuttgart, Pfaffenwaldring 47, D-70569, Germany
Hans-Joachim Wunderlich , ITI, Universität Stuttgart, Pfaffenwaldring 47, D-70569, Germany
pp. 39-44

DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systems (Abstract)

Michael A. Skitsas , KIOS Research Center, Department of ECE, University of Cyprus, Nicosia, Cyprus
Chrysostomos A. Nicopoulos , Department of ECE, University of Cyprus, Nicosia, Cyprus
Maria K. Michael , KIOS Research Center, Department of ECE, University of Cyprus, Nicosia, Cyprus
pp. 45-51

A novel scheme for concurrent error detection of OLS parallel decoders (Abstract)

Kazuteru Namba , Graduate School of Advanced Integration Science, Chiba University, JAPAN
Fabrizio Lombardi , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
pp. 52-57

Run-time mapping for reliable many-cores based on energy/performance trade-offs (Abstract)

C. Bolchini , Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria, Italy
M. Carminati , Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria, Italy
A. Miele , Politecnico di Milano, Dip. Elettronica, Informazione e Bioingegneria, Italy
A. Das , National University of Singapore, Dep. of Electrical and Computer Engineering, Singapore
A. Kumar , National University of Singapore, Dep. of Electrical and Computer Engineering, Singapore
B. Veeravalli , National University of Singapore, Dep. of Electrical and Computer Engineering, Singapore
pp. 58-64

Analysing degradation effects in charge-redistribution SAR ADCs (Abstract)

Muhammad Aamir Khan , Testable Design and Test of Integrated Systems (TDT) Group, University of Twente, Centre of Telematics and Information Technology (CTIT), Enschede, the Netherlands
Hans G. Kerkhoff , Testable Design and Test of Integrated Systems (TDT) Group, University of Twente, Centre of Telematics and Information Technology (CTIT), Enschede, the Netherlands
pp. 65-70

A cross-layer fault-tolerant design method for high manufacturing yield and system reliability (Abstract)

Jianghao Guo , School of Electronics and Computing Systems, University of Cincinnati, OH, USA
Qiang Han , School of Electronics and Computing Systems, University of Cincinnati, OH, USA
Wen-Ben Jone , School of Electronics and Computing Systems, University of Cincinnati, OH, USA
Yu-Liang Wu , Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T. Hong Kong
pp. 71-76

Fault Injection Framework for embedded memories (Abstract)

Patryk Skoncej , IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
pp. 77-82

A fast TCAD-based methodology for Variation analysis of emerging nano-devices (Abstract)

Hassan Ghasemzadeh Mohammadi , Integrated Systems Laboratory, EPFL, Lausanne, Switzerland
Pierre-Emmanuel Gaillardon , Integrated Systems Laboratory, EPFL, Lausanne, Switzerland
Majid Yazdani , IDIAP Laboratory, EPFL, Lausanne, Switzerland
Giovanni De Micheli , Integrated Systems Laboratory, EPFL, Lausanne, Switzerland
pp. 83-88

Low power and high speed current-mode memristor-based TLGs (Abstract)

Chandra Babu Dara , ECE Department, Southern Illinois University, Carbondale, USA
Themistoklis Haniotakis , ECE Department, Southern Illinois University, Carbondale, USA
Spyros Tragoudas , ECE Department, Southern Illinois University, Carbondale, USA
pp. 89-94

Approximate simulation of circuits with probabilistic behavior (Abstract)

Alexandru Paler , Faculty of Computer Science and Mathematics, University of Passau, Innstr. 43, D-94032, Germany
Josef Kinseher , Faculty of Computer Science and Mathematics, University of Passau, Innstr. 43, D-94032, Germany
Ilia Polian , Faculty of Computer Science and Mathematics, University of Passau, Innstr. 43, D-94032, Germany
John P. Hayes , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA
pp. 95-100

Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling (Abstract)

Chen Liu , Department of Electrical and Computer Engineering, University of Delaware, 140 Evans Hall, Newark, 19716, USA
Jeyavijayan Rajendran , Department of Electrical and Computer Engineering, Polytech Institute of New York University, Brooklyn, 11201, USA
Chengmo Yang , Department of Electrical and Computer Engineering, University of Delaware, 140 Evans Hall, Newark, 19716, USA
Ramesh Karri , Department of Electrical and Computer Engineering, Polytech Institute of New York University, Brooklyn, 11201, USA
pp. 101-106

F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments (Abstract)

Stefano Campitelli , Electronic Engineering Department, University of Rome “Tor Vergata”, Italy
Marco Ottavi , Electronic Engineering Department, University of Rome “Tor Vergata”, Italy
Salvatore Pontarelli , Electronic Engineering Department, University of Rome “Tor Vergata”, Italy
Alessandro Marchioro , CERN European Organization for Nuclear Research, Department: PH Group: ESE, 1211 Geneve 23, Switzerland
Daniele Felici , CERN European Organization for Nuclear Research, Department: PH Group: ESE, 1211 Geneve 23, Switzerland
Fabrizio Lombardi , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA
pp. 107-111

Evaluating CLB designs under multiple SETs in SRAM-based FPGAs (Abstract)

Arwa Ben Dhia , Institut TELECOM, TELECOM ParisTech, LTCI-CNRS, 46, rue Barrault 75634, France
Lirida Naviner , Institut TELECOM, TELECOM ParisTech, LTCI-CNRS, 46, rue Barrault 75634, France
Philippe Matherat , Institut TELECOM, TELECOM ParisTech, LTCI-CNRS, 46, rue Barrault 75634, France
pp. 112-117

Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling (Abstract)

Veit B. Kleeberger , Institute for Electronic Design Automation, Technische Universität München, Arcisstr. 21, 80333 Munich, Germany
Daniel Mueller-Gritschneder , Institute for Electronic Design Automation, Technische Universität München, Arcisstr. 21, 80333 Munich, Germany
Ulf Schlichtmann , Institute for Electronic Design Automation, Technische Universität München, Arcisstr. 21, 80333 Munich, Germany
pp. 118-124

Efficient compression of x-masking control data via dynamic channel allocation (Abstract)

Asad A. Bawa , Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, 78712-1084, USA
M. Tauseef Rab , Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, 78712-1084, USA
Nur A. Touba , Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, 78712-1084, USA
pp. 125-130

Synthesis of workload monitors for on-line stress prediction (Abstract)

Rafal Baranowski , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Alejandro Cook , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Michael E. Imhof , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Chang Liu , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Hans-Joachim Wunderlich , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
pp. 137-142

On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell (Abstract)

Elena I. Vatajelu , LIRMM, Montpellier, France
G. Tsiligiannis , LIRMM, Montpellier, France
L. Dilillo , LIRMM, Montpellier, France
A. Bosio , LIRMM, Montpellier, France
P. Girard , LIRMM, Montpellier, France
S. Pravossoudovitch , LIRMM, Montpellier, France
A. Todri , LIRMM, Montpellier, France
A. Virazel , LIRMM, Montpellier, France
F. Wrobel , Université Montpellier 2, France, IBS, UMR-CNRS 5214
F. Salgne , Université Montpellier 2, France, IBS, UMR-CNRS 5214
pp. 143-148

Robustness improvement of an SRAM cell against laser-induced fault injection (Abstract)

Alexandre Sarafianos , STMicroelectronics, Rousset, France
Mathieu Lisart , STMicroelectronics, Rousset, France
Olivier Gagliano , STMicroelectronics, Rousset, France
Valerie Serradeil , STMicroelectronics, Rousset, France
Cyril Roscian , Centre de Microelectronique de Provence - Georges, Charpak, Gardanne, France
Jean-Max Dutertre , Centre de Microelectronique de Provence - Georges, Charpak, Gardanne, France
Assia Tria , Centre de Microelectronique de Provence - Georges, Charpak, Gardanne, France
pp. 149-154

A low cost reliable architecture for S-Boxes in AES processors (Abstract)

Ting An , Institut Mines-Telecom, Telecom ParisTech, LTCI-CNRS, 46, rue Barrault 75634, France
Lirida Alves de Barros Naviner , Institut Mines-Telecom, Telecom ParisTech, LTCI-CNRS, 46, rue Barrault 75634, France
Philippe Matherat , Institut Mines-Telecom, Telecom ParisTech, LTCI-CNRS, 46, rue Barrault 75634, France
pp. 155-160

Variation-tolerant cache by two-layer error control codes (Abstract)

Meilin Zhang , Dept. of Electrical and Computer Engineering, University of Rochester, NY, 14627, USA
Paul Ampadu , Dept. of Electrical and Computer Engineering, University of Rochester, NY, 14627, USA
pp. 161-166

Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes (Abstract)

P. Reviriego , Universidad Antonio de Nebrija, Madrid, Spain
S. Liu , Universidad Antonio de Nebrija, Madrid, Spain
J.A. Maestro , Universidad Antonio de Nebrija, Madrid, Spain
S. Lee , Seoul National University of Science and Technology, Korea organization
N.A Touba , University of Texas at Austin, USA
R. Datta , University of Texas at Austin, USA
pp. 167-171

Improved image accuracy in Hot Pixel degraded digital cameras (Abstract)

Glenn H. Chapman , School of Engineering Science, Simon Fraser University, Burnaby, B.C., Canada, V5A 1S6
Rohit Thomas , School of Engineering Science, Simon Fraser University, Burnaby, B.C., Canada, V5A 1S6
Israel Koren , Dept. of Electrical and Computer Engineering, University of Massachusetts, Amherst, 01003, USA
Zahava Koren , Dept. of Electrical and Computer Engineering, University of Massachusetts, Amherst, 01003, USA
pp. 172-177

Impact of mid-bond testing in 3D stacked ICs (Abstract)

Mottaqiallah Taouil , Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD, The Netherlands
Said Hamdioui , Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD, The Netherlands
Erik Jan Marinissen , IMEC vzw, 3D Integration Program, Kapeldreef 75, 3001 Leuven, Belgium
Sudipta Bhawmik , Qualcomm, 5000 Somerset Corp. Blvd., Bridgewater, NJ, USA
pp. 178-183

Unified 3D test architecture for variable test data bandwidth across pre-bond, partial stack, and post-bond test (Abstract)

Yu-Wei Lee , Computer Engineering Research Center Department of Electrical and Computer Engineering University of Texas, Austin, 78712-1084, USA
Nur A. Touba , Computer Engineering Research Center Department of Electrical and Computer Engineering University of Texas, Austin, 78712-1084, USA
pp. 184-189

Analyzing circuit vulnerability to hardware Trojan insertion at the behavioral level (Abstract)

Hassan Salmani , Electrical and Computer Engineering, University of Connecticut, USA
Mohammed Tehranipoor , Electrical and Computer Engineering, University of Connecticut, USA
pp. 190-195

Secure Split-Test for preventing IC piracy by untrusted foundry and assembly (Abstract)

Gustavo K. Contreras , Dept. of Electrical & Computer Engineering, University of Connecticut, USA
Md. Tauhidur Rahman , Dept. of Electrical & Computer Engineering, University of Connecticut, USA
Mohammad Tehranipoor , Dept. of Electrical & Computer Engineering, University of Connecticut, USA
pp. 196-203

Differential analysis of Round-Reduced AES faulty ciphertexts (Abstract)

Amir-Pasha Mirbaha , Secure Systems and Architectures (SAS) Department, École Nationale Supérieure des Mines de Saint- Étienne, 13541 Gardanne, France
Jean-Max Dutertre , Secure Systems and Architectures (SAS) Department, École Nationale Supérieure des Mines de Saint- Étienne, 13541 Gardanne, France
Assia Tria , Secure Systems and Architectures (SAS) Department, CEA-Tech, 13541 Gardanne, France
pp. 204-211

Charge sharing aware NCL gates design (Abstract)

Matheus T. Moreira , GAPH - Faculty of Computer Science - PUCRS - Porto Alegre - RS - Brazil
Bruno S. Oliveira , GAPH - Faculty of Computer Science - PUCRS - Porto Alegre - RS - Brazil
Fernando G. Moraes , GAPH - Faculty of Computer Science - PUCRS - Porto Alegre - RS - Brazil
Ney L. V. Calazans , GAPH - Faculty of Computer Science - PUCRS - Porto Alegre - RS - Brazil
pp. 212-217

Reliability analysis of combinational circuits with the influences of noise and single-event transients (Abstract)

Kaikai Liu , Institut Mines-TELECOM, TELECOM-ParisTech, LTCI-CNRS, 46 Rue Barrault, 75013, France
Hao Cai , Institut Mines-TELECOM, TELECOM-ParisTech, LTCI-CNRS, 46 Rue Barrault, 75013, France
Ting An , Institut Mines-TELECOM, TELECOM-ParisTech, LTCI-CNRS, 46 Rue Barrault, 75013, France
Lirida Naviner , Institut Mines-TELECOM, TELECOM-ParisTech, LTCI-CNRS, 46 Rue Barrault, 75013, France
Jean-Francois Naviner , Institut Mines-TELECOM, TELECOM-ParisTech, LTCI-CNRS, 46 Rue Barrault, 75013, France
Herve Petit , Institut Mines-TELECOM, TELECOM-ParisTech, LTCI-CNRS, 46 Rue Barrault, 75013, France
pp. 218-223

Online TSV health monitoring and built-in self-repair to overcome aging (Abstract)

Caleb Serafy , Department of Electrical and Computer Engineering, University of Maryland, College Park, 20742, USA
Ankur Srivastava , Department of Electrical and Computer Engineering, University of Maryland, College Park, 20742, USA
pp. 224-229

Impact of PVT variation on delay test of resistive open and resistive bridge defects (Abstract)

Shida Zhong , School of ECS, University of Southampton, UK
Saqib Khursheed , School of ECS, University of Southampton, UK
Bashir M. Al-Hashimi , School of ECS, University of Southampton, UK
pp. 230-235

SmartInjector: Exploiting intelligent fault injection for SDC rate analysis (Abstract)

Jianli Li , School of Computer, National University of Defense Technology, China
Qingping Tan , School of Computer, National University of Defense Technology, China
pp. 236-242

Built-in Self-Repair in a 3D die stack using programmable logic (Abstract)

Kundan Nepal , School of Engineering, University of St Thomas, St Paul, MN, USA
Xi Shen , Department of Computer Science and Engineering, Southern Methodist University, Dallas, TX, USA
Jennifer Dworak , Department of Computer Science and Engineering, Southern Methodist University, Dallas, TX, USA
Theodore Manikas , Department of Computer Science and Engineering, Southern Methodist University, Dallas, TX, USA
R. Iris Bahar , School of Engineering, Brown University, Providence, RI, USA
pp. 243-248

Spare sharing network enhancement for scalable systems (Abstract)

Soroush Khaleghi , ECE Department, University of Illinois at Chicago, 60607, USA
Wenjing Rao , ECE Department, University of Illinois at Chicago, 60607, USA
pp. 249-254

Automated integration of fault injection into the ASIC design flow (Abstract)

Aleksandar Simevski , Brandenburg University of Technology, Konrad-Wachsmann-Allee 1, D-03046 Cottbus, Germany
Rolf Kraemer , Brandenburg University of Technology, Konrad-Wachsmann-Allee 1, D-03046 Cottbus, Germany
Milos Krstic , IHP, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany
pp. 255-260

Modeling and analysis of repair and maintenance processes in Fault Tolerant Systems (Abstract)

J.-Y. Hung , Oklahoma City University, 73106, Department of Computer Science, USA
N.-J. Park , Department of Computer Science, Oklahoma State University, Stillwater, 74078-1053, USA
K.M. George , Oklahoma City University, 73106, Department of Computer Science, USA
N. Park , Oklahoma City University, 73106, Department of Computer Science, USA
pp. 261-265

Exploiting error control approaches for Hardware Trojans on Network-on-Chip links (Abstract)

Qiaoyan Yu , Department of Electrical and Computer Engineering, University of New Hampshire, Durham, 03824, USA
Jonathan Frey , Department of Electrical and Computer Engineering, University of New Hampshire, Durham, 03824, USA
pp. 266-271

Framework for dynamic estimation of power-supply noise and path delay (Abstract)

Sushmita Kadiyala Rao , CSEE Department, University of Maryland, Baltimore County, USA
Ryan Robucci , CSEE Department, University of Maryland, Baltimore County, USA
Chintan Patel , CSEE Department, University of Maryland, Baltimore County, USA
pp. 272-277

A smart Trojan circuit and smart attack method in AES encryption circuits (Abstract)

Masayoshi Yoshimura , Graduate School of Information Science and Electrical Engineering, Kyushu University, Nishi-ku, Fukuoka 819-0395, Japan
Amy Ogita , Graduate School of Industrial Technology, Nihon University, Japan
Toshinori Hosokawa , College of Industrial Technology, Nihon University, Japan
pp. 278-283

On-chip error correction with unreliable decoders: Fundamental physical limits (Abstract)

Natesh Ganesh , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, 01003-9292, USA
Neal G. Anderson , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, 01003-9292, USA
pp. 284-289

Reconfigurable distributed fault tolerant routing algorithm for on-chip networks (Abstract)

Manoj Kumar , Department of Computer Engineering, Malaviya National Institute of Technology, Jaipur, India
Pankaj , Department of Computer Engineering, Malaviya National Institute of Technology, Jaipur, India
Vijay Laxmi , Department of Computer Engineering, Malaviya National Institute of Technology, Jaipur, India
Manoj Singh Gaur , Department of Computer Engineering, Malaviya National Institute of Technology, Jaipur, India
Seok-Bum Ko , Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, Canada
pp. 290-295

BIST for logic and local interconnect resources in a novel mesh of cluster FPGA (Abstract)

Saif-Ur Rehman , TIMA Laboratory (INP-Grenoble, UJF, CNRS), France
Mounir Benabdenbi , TIMA Laboratory (INP-Grenoble, UJF, CNRS), France
Lorena Anghel , TIMA Laboratory (INP-Grenoble, UJF, CNRS), France
pp. 296-301

Testing of switch blocks in TSV-reduced Three-Dimensional FPGA (Abstract)

Kouta Maebashi , Graduate School of Advanced Integration Science, Chiba University, 1-33 Yayoicho, Inage-ku, Chiba-shi, 263-8522, JAPAN
Kazuteru Namba , Graduate School of Advanced Integration Science, Chiba University, 1-33 Yayoicho, Inage-ku, Chiba-shi, 263-8522, JAPAN
Masato Kitakami , Graduate School of Advanced Integration Science, Chiba University, 1-33 Yayoicho, Inage-ku, Chiba-shi, 263-8522, JAPAN
pp. 302-307
92 ms
(Ver 3.3 (11022016))