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2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2017)
Cambridge, United Kingdom
Oct. 23, 2017 to Oct. 25, 2017
ISSN: 2377-7966
ISBN: 978-1-5386-0363-5
TABLE OF CONTENTS

Front cover (PDF)

pp. 1

Welcome message (PDF)

pp. iii-v

Contents (PDF)

pp. x-xii

Author index (PDF)

pp. 181-182

Lifetime memory reliability data from the field (Abstract)

Taniya Siddiqua , RAS Architecture, Advanced Micro Devices, Inc.
Vilas Sridharan , RAS Architecture, Advanced Micro Devices, Inc.
Steven E. Raasch , AMD Research
Nathan DeBardeleben , Ultrascale Systems Research Center, Los Alamos National Laboratory
Kurt B. Ferreira , Center for Computing Research, Sandia National Laboratories
Scott Levy , Center for Computing Research, Sandia National Laboratories
Elisabeth Baseman , Ultrascale Systems Research Center, Los Alamos National Laboratory
Qiang Guan , Ultrascale Systems Research Center, Los Alamos National Laboratory
pp. 1-6

High-yield design of high-density SRAM for low-voltage and low-leakage operations (Abstract)

Kedar Janardan Dhori , STMicroelectronics Pvt. Ltd., Greater Noida, India
Hitesh Chawla , STMicroelectronics Pvt. Ltd., Greater Noida, India
Ashish Kumar , STMicroelectronics Pvt. Ltd., Greater Noida, India
Prashant Pandey , STMicroelectronics Pvt. Ltd., Greater Noida, India
Promod Kumar , STMicroelectronics Pvt. Ltd., Greater Noida, India
Lorenzo Ciampolini , CEA Grenoble
Florian Cacho , STMicroelectronics, Crolles, France
Damien Croain , STMicroelectronics, Crolles, France
pp. 1-6

Investigating the effects of process variations and system workloads on endurance of non-volatile caches (Abstract)

Amir Mahdi Hosseini Monazzah , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
Hamed Farbeh , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
Seyed Ghassem Miremadi , Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
pp. 1-6

Towards SRAM leakage power minimization by aggressive standby voltage scaling — Experiments on 40nm test chips (Abstract)

Xin Fan , Holst-Center/IMEC-NL, Eindhoven, Netherlands
Jan Stuijt , Holst-Center/IMEC-NL, Eindhoven, Netherlands
Tobias Gemmeke , Holst-Center/IMEC-NL, Eindhoven, Netherlands
pp. 1-4

RASSS: A perfidy-aware protocol for designing trustworthy distributed systems (Abstract)

Lake Bu , Adaptive and Secure Computing Systems Laboratory, Boston University, Boston, USA
Hien D. Nguyen , Adaptive and Secure Computing Systems Laboratory, Boston University, Boston, USA
Michel A. Kinsy , Adaptive and Secure Computing Systems Laboratory, Boston University, Boston, USA
pp. 1-6

Realizing strong PUF from weak PUF via neural computing (Abstract)

Leandro Santiago , Programa de Engenharia de Sistemas e Computação - COPPE Universidade Federal do Rio de Janeiro (UFRJ), Brazil
Vinay C. Patil , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Charles B. Prado , National Institute of Metrology, Quality and Technology (Inmetro), Brazil
Tiago A. O. Alves , Programa de Engenharia de Sistemas e Computação - COPPE Universidade Federal do Rio de Janeiro (UFRJ), Brazil
Leandro A. J. Marzulo , Instituto de Matemática e Estatística Universidade do Estado do Rio de Janeiro (UERJ), Brazil
Felipe M. G. Franca , Programa de Engenharia de Sistemas e Computação - COPPE Universidade Federal do Rio de Janeiro (UFRJ), Brazil
Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
pp. 1-6

Preventing scan-based side-channel attacks through key masking (Abstract)

Satyadev Ahlawat , Computer Architecture & Dependable Systems Lab, Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, India
Darshit Vaghani , Computer Architecture & Dependable Systems Lab, Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, India
Virendra Singh , Computer Architecture & Dependable Systems Lab, Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, India
pp. 1-4

Hardware and software innovations in energy-efficient system-reliability monitoring (Abstract)

Vasileios Tenentes , ECS, University of Southampton, UK
Charles Leech , ECS, University of Southampton, UK
Graeme M. Bragg , ECS, University of Southampton, UK
Geoff Merrett , ECS, University of Southampton, UK
Bashir M. Al-Hashimi , ECS, University of Southampton, UK
Hussam Amrouch , Karlsruhe Institute of Technology, Karlsruhe, Germany
Jorg Henkel , Karlsruhe Institute of Technology, Karlsruhe, Germany
Shidhartha Das , ARM, Cambridge, UK
pp. 1-5

Eliminating a hidden error source in stochastic circuits (Abstract)

Paishun Ting , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109, USA
John P. Hayes , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109, USA
pp. 1-6

Simulation-based evaluation of frequency upscaled operation of exact/approximate ripple carry adders (Abstract)

H Junqi , Dept. of Electrical and Electronic Eng., The University of Nottingham, Selangor, Malaysia
T. Nandha Kumar , Dept. of Electrical and Electronic Eng., The University of Nottingham, Selangor, Malaysia
Haider Abbas , Dept. of Electrical and Electronic Eng., The University of Nottingham, Selangor, Malaysia
Fabrizio Lombardi , Dept. of Electrical and Computer Eng., Northeastern University, Boston, MA 02115
pp. 1-6

CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design (Abstract)

Sina Boroumand , University of Tehran, Tehran, Iran
Hadi P. Afshar , Qualcomm Research, San Diego, USA
Philip Brisk , University of California, Riverside, Riverside, USA
Siamak Mohammadi , University of Tehran, Tehran, Iran
pp. 1-6

Kernel vulnerability factor and efficient hardening for histogram of oriented gradients (Abstract)

Lucas Weigel , Institute of Informatics, Federal University of Rio Grande do Sul
Fernando Fernandes , Institute of Informatics, Federal University of Rio Grande do Sul
Philippe Navaux , Institute of Informatics, Federal University of Rio Grande do Sul
Paolo Rech , Institute of Informatics, Federal University of Rio Grande do Sul
pp. 1-6

A dynamic reliability management framework for heterogeneous multicore systems (Abstract)

Alessandro Baldassari , Dip. Elettronica, Informazione e Bioingegneria - Politecnico di Milano, Italy
Cristiana Bolchini , Dip. Elettronica, Informazione e Bioingegneria - Politecnico di Milano, Italy
Antonio Miele , Dip. Elettronica, Informazione e Bioingegneria - Politecnico di Milano, Italy
pp. 1-6

A scrubbing scheduling approach for reliable FPGA multicore processors with real-time constraints (Abstract)

Mihalis Psarakis , Department of Informatics, University of Piraeus, Greece
Aitzan Sari , Department of Informatics, University of Piraeus, Greece
pp. 1-4

Region based containers — A new paradigm for the analysis of fault tolerant networks (Abstract)

Prashant D. Joshi , Cadence Design Systems, Austin, Texas 78759
Arunabha Sen , School of CIDSE, Arizona State University, Tempe, AZ 85281
D. Frank Hsu , Department of Computer and Information Sciences, Fordham University, New York, New York 10458
Said Hamdioui , Computer Engineering Laboratory, TU Delft, Delft, The Netherlands
Koen Bertels , Computer Engineering Laboratory, TU Delft, Delft, The Netherlands
pp. 1-4

On-line software-based self-test for ECC of embedded RAM memories (Abstract)

M. Restifo , Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy
P. Bernardi , Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy
S. De Luca , STMicroelectronics, Agrate Brianza, Italy
A. Sansonetti , STMicroelectronics, Agrate Brianza, Italy
pp. 1-6

On the optimization of SBST test program compaction (Abstract)

R. Cantora , Politecnico di Torino, Dip. Automatica e Informatica, Torino, Italy
E. Sanchez , Politecnico di Torino, Dip. Automatica e Informatica, Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Dip. Automatica e Informatica, Torino, Italy
G. Squillero , Politecnico di Torino, Dip. Automatica e Informatica, Torino, Italy
E. Valea , Politecnico di Torino, Dip. Automatica e Informatica, Torino, Italy
pp. 1-4

Low cost error monitoring for improved maintainability of IoT applications (Abstract)

Mauricio D. Gutierrez , University of Southampton, UK
Vasileios Tenentes , University of Southampton, UK
Tom J. Kazmierski , University of Southampton, UK
Daniele Rossi , University of Westminster, UK
pp. 1-6

A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type (Abstract)

Michiya Kanda , Graduate School of Technology, Industrial and Social Sciences, Tokushima University, Tokushima, 770-8506, Japan
Masaki Hashizume , Graduate School of Technology, Industrial and Social Sciences, Tokushima University, Tokushima, 770-8506, Japan
Hiroyuki Yotsuyanagi , Graduate School of Technology, Industrial and Social Sciences, Tokushima University, Tokushima, 770-8506, Japan
Shyue-Kung Lu , College of Electrical Engineering and Computer Science, National Taiwan Univ. of Science and Technology, Taipei, 106, Taiwan(R.O.C.)
pp. 1-4

Volume management for fault-tolerant continuous-flow microfluidics (Abstract)

Alexander Schneider , DTU Compute, Tecnical University of Denmark
Paul Pop , DTU Compute, Tecnical University of Denmark
Jan Madsen , DTU Compute, Tecnical University of Denmark
pp. 1

Design-for-testability for paper-based digital microfluidic biochips (Abstract)

Jian-De Li , Department of Computer Science and Engineering, National Chung Hsing University, Taichung, Taiwan
Sying-Jyan Wang , Department of Computer Science and Engineering, National Chung Hsing University, Taichung, Taiwan
Katherine Shu-Min Li , Department of Computer Science and Engineering, National Chung Hsing University, Taichung, Taiwan
Tsung-Yi Ho , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan
pp. 1

Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs) (Abstract)

Bing Li , Chair of Electronic Design Automation, Technical University of Munich, Germany
Ulf Schlichtmann , Chair of Electronic Design Automation, Technical University of Munich, Germany
pp. 1

A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips (Abstract)

V Gokulkrishnan , Department of CSE, Indian Institute of Technology, Madras
V Kamakoti , Department of CSE, Indian Institute of Technology, Madras
Nitin Chandrachoodan , Department of Electrical Engineering, Indian Institute of Technology, Madras
Seetal Potluri , Xilinx Singapore
pp. 1-4

Early estimation of aging in the design flow of integrated circuits through a programmable hardware module (Abstract)

Chiara Sandionigi , CEA, LIST, F-91191 Gif sur Yvette, France
Mauricio Altieri , Univ. Grenoble Alpes, CEA, LETI, 38000 Grenoble, France
Olivier Heron , CEA, LIST, F-91191 Gif sur Yvette, France
pp. 1-6

Lifetime reliability characterization of N/MEMS used in power gating of digital integrated circuits (Abstract)

Haider Alrudainy , School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne, NE1 7RU, UK
Rishad Shafik , School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne, NE1 7RU, UK
Andrey Mokhov , School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne, NE1 7RU, UK
Alex Yakovlev , School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne, NE1 7RU, UK
pp. 1-6

Unintrusive aging analysis based on offline learning (Abstract)

Frank Sill Torres , Dept. of Electronic Engineering, Universidade Federal de Minas Gerias, Belo Horizonte, Brazil
Pedro Fausto Rodrigues Leite , Institute of Computer Science, University of Bremen, Bremen, Germany
Rolf Drechsler , Cyber-Physical Systems DFKI GmbH Bremen, Germany
pp. 1-4

REMORA: A hybrid low-cost soft-error reliable fault tolerant architecture (Abstract)

Shoba Gopalakrishnan , CADSL, Indian Institute of Technology Bombay, India
Virendra Singh , CADSL, Indian Institute of Technology Bombay, India
pp. 1-6

Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems (Abstract)

Nguyen T. H. Nguyen , School of Computer Science and Engineering, UNSW Australia
Ediz Cetin , Department of Engineering, Macquarie University, Australia
Oliver Diessel , School of Computer Science and Engineering, UNSW Australia
pp. 1-4

High-energy neutrons characterization of a safety critical computing system (Abstract)

Andrea Fedi , Neat S.r.l., Rome, Italy
Marco Ottavi , University of Rome Tor Vergata, Department of Electronic Engineering, Rome, Italy
Gianluca Furano , ESTEC - ESA (European Space Agency), Keplerlaan 1 2201AZ Noordwijk, The Netherlands
Antimo Bruno , Neat S.r.l., Rome, Italy
Roberto Senesi , University of Rome Tor Vergata, Department of Physics, Rome, Italy
Carla Andreani , University of Rome Tor Vergata, Department of Physics, Rome, Italy
Carlo Cazzaniga , Rutherford Appleton Laboratory-ISIS, Didcot, Oxon OX11 0QX, U.K.
pp. 1-4

Exploring soft errors (SEUs) with digital imager pixels ranging from 7 to 1.3 μm (Abstract)

Glenn H. Chapman , School of Engineering Science, Simon Fraser University, Burnaby, B.C., Canada, V5A 1S6
Parham Purbakht , School of Engineering Science, Simon Fraser University, Burnaby, B.C., Canada, V5A 1S6
Peter Le , School of Engineering Science, Simon Fraser University, Burnaby, B.C., Canada, V5A 1S6
Israel Koren , Dept. of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, 01003
Zahava Koren , Dept. of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, 01003
pp. 1-4

Detecting errors in instructions with bloom filters (Abstract)

Mert Atamaner , Department of Computer Engineering, TOBB university of Economics and Technology, 06560 Ankara, Turkey
Oguz Ergin , Department of Computer Engineering, TOBB university of Economics and Technology, 06560 Ankara, Turkey
Marco Ottavi , Department of Electronic Engineering, University of Rome Tor Vergata, 00133 Rome, Italy
Pedro Reviriego , ARIES Research center, Universidad Antonio de Nebrija, C. Pirineos 55, 28040 Madrid, Spain
pp. 1-4

High performance fault tolerance through predictive instruction re-execution (Abstract)

Jyothish Soman , Computer Laboratory, University of Cambridge
Timothy M. Jones , Computer Laboratory, University of Cambridge
pp. 1-4

A resilient scheduler for dataflow execution (Abstract)

Tiago A. O. Alves , Instituto de Matematica e Estatística, Universidade do Estado do Rio de Janeiro (UERJ), Rio de Janeiro, Brazil
Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts Amherst
Leandro A. J. Marzulo , Instituto de Matematica e Estatística, Universidade do Estado do Rio de Janeiro (UERJ), Rio de Janeiro, Brazil
Felipe M. G. Franca , Programa de Engenharia de Sistemas e Computação - COPPE, Universidade Federal do Rio de Janeiro (UFRJ), Rio de Janeiro, Brazil
pp. 1-4

A novel low-overhead fault tolerant parallel-pipelined FFT design (Abstract)

Yu Xie , Beijing Key Laboratory of Embedded Real-time Information Processing Technology, Beijing Institute of Technology, Beijing, China
Chen Yang , Beijing Key Laboratory of Embedded Real-time Information Processing Technology, Beijing Institute of Technology, Beijing, China
Chuang-An Mao , Beijing Key Laboratory of Embedded Real-time Information Processing Technology, Beijing Institute of Technology, Beijing, China
He Chen , Beijing Key Laboratory of Embedded Real-time Information Processing Technology, Beijing Institute of Technology, Beijing, China
Yi-Zhuang Xie , Beijing Key Laboratory of Embedded Real-time Information Processing Technology, Beijing Institute of Technology, Beijing, China
pp. 1-4

Reconfigurable TAP controllers with embedded compression for large test data volume (Abstract)

Sebastian Huhn , University of Bremen, Germany
Stephan Eggersglus , University of Bremen, Germany
Rolf Drechsler , University of Bremen, Germany
pp. 1-6

A dynamic test compaction method on low power test generation based on capture safe test vectors (Abstract)

Toshinori Hosokawa , College of Industrial Technology, Nihon University, Chiba, Japan
Atsushi Hirai , Graduate School of Industrial Technology, Nihon University, Chiba, Japan
Hiroshi Yamazaki , College of Industrial Technology, Nihon University, Chiba, Japan
Masayuki Arai , College of Industrial Technology, Nihon University, Chiba, Japan
pp. 1-6

Machine learning based test pattern analysis for localizing critical power activity areas (Abstract)

Harshad Dhotre , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
Stephan Eggersglus , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
Mehdi Dehbashi , Infineon Technologies AG, Munich, Germany
Ulrike Pfannkuchen , Infineon Technologies AG, Munich, Germany
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
pp. 1-6

Improving test compression with multiple-polynomial LFSRs (Abstract)

Yu-Wei Lee , Computer Engineering Research Center, University of Texas, Austin, TX 78712
Nur A. Touba , Computer Engineering Research Center, University of Texas, Austin, TX 78712
pp. 1-4
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