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2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2016)
Storrs, CT, USA
Sept. 19, 2016 to Sept. 20, 2016
ISSN: 2377-7966
ISBN: 978-1-5090-3624-0
TABLE OF CONTENTS

[Front cover] (PDF)

pp. c1

Foreword (PDF)

Omer Khan , University of Connecticut, USA
Maria K. Michael , University of Cyprus, Cyprus
Antonio Miele , Politecnico di Milano, Italy
Qiaoyan Yu , University of New Hampshire, USA
pp. iii

Table of contents (PDF)

pp. v-vii

Author index (PDF)

pp. 158-159

BTI aware thermal management for reliable DVFS designs (Abstract)

Hardeep Chahal , ECS, University of Southampton, UK
Vasileios Tenentes , ECS, University of Southampton, UK
Daniele Rossi , ECS, University of Southampton, UK
Bashir M. Al-Hashimi , ECS, University of Southampton, UK
pp. 1-6

Prognosis of NBTI aging using a machine learning scheme (Abstract)

Naghmeh Karimi , Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ 08854, United States
Ke Huang , Department of Electrical and Computer Engineering, San Diego State University, CA 92182, United States
pp. 7-10

Experimental study and analysis of soft and permanent errors in digital cameras (Abstract)

Glenn H. Chapman , School of Engineering Science, Simon Fraser University, Burnaby, B.C., Canada, V5A 1S6
Rahul Thomas , School of Engineering Science, Simon Fraser University, Burnaby, B.C., Canada, V5A 1S6
Rohan Thomas , School of Engineering Science, Simon Fraser University, Burnaby, B.C., Canada, V5A 1S6
Israel Koren , Dept. of Electrical and Computer Engineering, University of Massachusetts, Amherst, 01003, United States
Zahava Koren , Dept. of Electrical and Computer Engineering, University of Massachusetts, Amherst, 01003, United States
pp. 11-14

A Highly Robust Double Node Upset Tolerant latch (Abstract)

Adam Watkins , Los Alamos National Laboratories, NM 87545, United States
Spyros Tragouodas , Southern Illinois Univeristy Carbondale, 62901, United States
pp. 15-20

Applying efficient fault tolerance to enable the preconditioned conjugate gradient solver on approximate computing hardware (Abstract)

Alexander Scholl , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, D-70569, Germany
Claus Braun , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, D-70569, Germany
Hans-Joachim Wunderlich , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, D-70569, Germany
pp. 21-26

Construction of a soft error (SEU) hardened Latch with high critical charge (Abstract)

Hiroki Ueno , Graduate School of Advanced Integration Science, Chiba University, 1-33 Yayoi-cho, Inage-ku, Chiba-shi, 263-8522 Japan
Kazuteru Namba , Graduate School of Advanced Integration Science, Chiba University, 1-33 Yayoi-cho, Inage-ku, Chiba-shi, 263-8522 Japan
pp. 27-30

Design and analysis of an approximate 2D convolver (Abstract)

Ke Chen , Electrical and Computer Engineering Department, Northeastern University, Boston, USA
Fabrizio Lombardi , Electrical and Computer Engineering Department, Northeastern University, Boston, USA
Jie Han , Electrical and Computer Engineering Department, University of Alberta, Edmonton, Canada
pp. 31-34

Combined on-line lifetime-energy optimization for asymmetric multicores (Abstract)

Cristiana Bolchini , Dipartimento di Elettronica, Informazione e Bioiongegneria, Politecnico di Milano, Italy
Matteo Carminati , Dipartimento di Elettronica, Informazione e Bioiongegneria, Politecnico di Milano, Italy
Tulika Mitra , School of Computing, National University of Singapore - Singapore
Thannirmalai Somu Muthukaruppan , School of Computing, National University of Singapore - Singapore
pp. 35-40

Effects of online fault detection mechanisms on Probabilistic Timing Analysis (Abstract)

Chao Chen , École Polytechnique de Montréal, Canada
Jacopo Panerati , École Polytechnique de Montréal, Canada
Giovanni Beltrame , École Polytechnique de Montréal, Canada
pp. 41-46

Bounding error detection latency in safety critical systems with enhanced Execution Fingerprinting (Abstract)

Mojing Liu , Department of Electrical and Computer Engineering, McGill University, Montréal, Québec, Canada
Brett H. Meyer , Department of Electrical and Computer Engineering, McGill University, Montréal, Québec, Canada
pp. 47-52

Guiding Genetic Algorithms using importance measures for reliable design of embedded systems (Abstract)

Hananeh Aliee , Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
Stefan Vitzethum , Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
Michael Glass , Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
Jurgen Teich , Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
Emanuele Borgonovo , Bocconi University, Milan, Italy
pp. 53-56

Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures (Abstract)

Zaid Al-bayati , McGill University, Montreal, Canada
Brett H. Meyer , McGill University, Montreal, Canada
Haibo Zeng , Virginia Tech, Blacksburg, USA
pp. 57-62

Cross-layer fault-tolerant design of real-time systems (Abstract)

Siva Satyendra Sahoo , National University of Singapore, Department of Electrical and Computer Engineering, Singapore
Bharadwaj Veeravalli , National University of Singapore, Department of Electrical and Computer Engineering, Singapore
Akash Kumar , Technische Universität Dresdenm, Center for Advancing Electronics Dresden (cfaed), Germany
pp. 63-68

Fault-aware sensitivity analysis for probabilistic real-time systems (Abstract)

Luca Santinelli , UFTMIP ONERA Toulouse, France
Zhishan Guo , Missouri University of Science and Technology, United States
Laurent George , University of Paris Est / LIGM - ESIEE Paris, France
pp. 69-74

Low cost resilient regular expression matching on FPGAs (Abstract)

Marcos T. Leipnitz , Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Eduardo Nunes de Souza , Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Gabriel L. Nazar , Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
pp. 75-80

In-place LUT polarity inVersion to mitigate soft errors for FPGAs (Abstract)

Juexiao Su , EE Dept., Univeristy of California, Los Angeles, United States
Ju-Yueh Lee , EE Dept., Univeristy of California, Los Angeles, United States
Chang Wu , State Key Laboratory of ASIC & System, Fudan University, China
Lei He , EE Dept., Univeristy of California, Los Angeles, United States
pp. 81-86

Detecting intermittent resistive faults in digital CMOS circuits (Abstract)

Hassan Ebrahimi , Testable Design and Test of Integrated Systems (TDT) Group, University of Twente, Centre for Telematics and Information Technology (CTIT), Enschede, the Netherlands
Alireza Rohani , Testable Design and Test of Integrated Systems (TDT) Group, University of Twente, Centre for Telematics and Information Technology (CTIT), Enschede, the Netherlands
Hans G. Kerkhoff , Testable Design and Test of Integrated Systems (TDT) Group, University of Twente, Centre for Telematics and Information Technology (CTIT), Enschede, the Netherlands
pp. 87-90

Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU (Abstract)

Xabier Iturbe , ARM Research, Cambridge, UK
Balaji Venu , ARM Research, Cambridge, UK
Emre Ozer , ARM Research, Cambridge, UK
pp. 91-96

Efficient utilization of hierarchical iJTAG networks for interrupts management (Abstract)

Ahmed Ibrahim , Testable Design and Test of Integrated Systems Group (TDT), Centre of Telematics and Information Technology (CTIT), University of Twente, Enschede, the Netherlands
Hans G. Kerkhoff , Testable Design and Test of Integrated Systems Group (TDT), Centre of Telematics and Information Technology (CTIT), University of Twente, Enschede, the Netherlands
pp. 97-102

Error recovery through partial value similarity (Abstract)

Abdulaziz Eker , Department of Computer Engineering, TOBB University of Economics and Technology, Ankara, Turkey
Oguz Ergin , Department of Computer Engineering, TOBB University of Economics and Technology, Ankara, Turkey
pp. 103-106

In-field functional test programs development flow for embedded FPUs (Abstract)

R. Cantoro , Politecnico di Torino - Dipartimento di Automatica e Informatica - Italy
D. Piumatti , Politecnico di Torino - Dipartimento di Automatica e Informatica - Italy
P. Bernardi , Politecnico di Torino - Dipartimento di Automatica e Informatica - Italy
S. De Luca , STMicroelectronics, Italy
A. Sansonetti , STMicroelectronics, Italy
pp. 107-110

Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams (Abstract)

Filippo Giuliani , NEAT S.r.l. Rome, Italy
Marco Ottavi , University of Rome Tor Vergata, Department of Electronic Engineering, Italy
Gian Carlo Cardarilli , University of Rome Tor Vergata, Department of Electronic Engineering, Italy
Marco Re , University of Rome Tor Vergata, Department of Electronic Engineering, Italy
Luca Di Nunzio , University of Rome Tor Vergata, Department of Electronic Engineering, Italy
Rocco Fazzolari , University of Rome Tor Vergata, Department of Electronic Engineering, Italy
Antimo Bruno , NEAT S.r.l. Rome, Italy
Francesco Zuliani , NEAT S.r.l. Rome, Italy
pp. 111-114

CoBRA: Low cost compensation of TSV failures in 3D-NoC (Abstract)

Ronak Salamat , University of California, Irvine, United States of America
Masoumeh Ebrahimi , KTH Royal Institute of Technology and University of Turku, Finland
Nader Bagherzadeh , University of California, Irvine, United States of America
Freek Verbeek , Open University of The Netherlands, Radboud University, Nijmegen, The Netherlands
pp. 115-120

A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs (Abstract)

Amir Charif , TIMA Laboratory, Grenoble INP, France
Nacer-Eddine Zergainoh , TIMA Laboratory, Grenoble INP, France
Michael Nicolaidis , TIMA Laboratory, Grenoble INP, France
pp. 121-126

An adaptive routing algorithm to improve lifetime reliability in NoCs architecture (Abstract)

Juman Alshraiedeh , Department of Electrical Engineering and Computer Science, Russ College of Engineering and Technology, Ohio University, 322D Stocker Center, Athens, 45701, United States of America
Avinash Kodi , Department of Electrical Engineering and Computer Science, Russ College of Engineering and Technology, Ohio University, 322D Stocker Center, Athens, 45701, United States of America
pp. 127-130

A novel method for SEE validation of complex SoCs using Low-Energy Proton beams (Abstract)

Gianluca Furano , European Space Agency, European Space Technology Centre, Noordwijk, The Netherlands
Stefano Di Mascio , University of Rome Tor Vergata, Department of Electronic Engineering, Rome, Italy
Tomasz Szewczyk , European Space Agency, European Space Technology Centre, Noordwijk, The Netherlands
Alessandra Menicucci , Delft University of Technology, Faculty of Aerospace Engineering, Space Systems Engineering, The Netherlands
Luigi Campajola , University of Naples Federico II, Department of Physics E. Pancini, Naples, Italy
Francesco Di Capua , University of Naples Federico II, Department of Physics E. Pancini, Naples, Italy
Andrea Fabbri , INFN, Roma Tre Section, Rome, Italy
Marco Ottavi , University of Rome Tor Vergata, Department of Electronic Engineering, Rome, Italy
pp. 131-134

Reliable PUF design using failure patterns from time-controlled power gating (Abstract)

Xiaolin Xu , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, United States of America
Daniel E. Holcomb , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, United States of America
pp. 135-140

Side channel attacks on STTRAM and low-overhead countermeasures (Abstract)

Anirudh Iyengar , Pennsylvania State University, United States of America
Swaroop Ghosh , Pennsylvania State University, United States of America
Nitin Rathi , Purdue University, United States of America
Helia Naeimi , Intel Corp., United States of America
pp. 141-146

On meta-obfuscation of physical layouts to conceal design characteristics (Abstract)

Vinay C. Patil , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, USA
Arunkumar Vijayakumar , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, USA
Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, USA
pp. 147-152

Can flexible, domain specific programmable logic prevent IP theft? (Abstract)

Xiaotong Cui , College of Computer Science, Chongqing University, China
Kaijie Wu , Tandon School of Engineering, New York University, United States of America
Siddharth Garg , Tandon School of Engineering, New York University, United States of America
Ramesh Karri , Tandon School of Engineering, New York University, United States of America
pp. 153-157
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