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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2012)
Austin, TX, USA USA
Oct. 3, 2012 to Oct. 5, 2012
ISSN: 1550-5774
ISBN: 978-1-4673-3043-5
TABLE OF CONTENTS
Papers

[Front matter] (Abstract)

pp. i-ix

[Front matter] (PDF)

pp. i-ix
Papers

Path-delay fingerprinting for identification of recovered ICs (Abstract)

Xuehui Zhang , ECE, University of Connecticut
Kan Xiao , ECE, University of Connecticut
Mohammad Tehranipoor , ECE, University of Connecticut
pp. 13-18

Using partial masking in X-chains to increase output compaction for an X-canceling MISR (Abstract)

Nur A. Touba , Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712-1084
Asad A. Bawa , Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712-1084
M. Tauseef Rab , Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712-1084
pp. 19-24

On the development of Software-Based Self-Test methods for VLIW processors (Abstract)

D. Sabena , Dipartimento di Automatica e Informatica, Politecnico di Tonno, Torino, Italy
M. Sonza Reorda , Dipartimento di Automatica e Informatica, Politecnico di Tonno, Torino, Italy
L. Sterpone , Dipartimento di Automatica e Informatica, Politecnico di Tonno, Torino, Italy
pp. 25-30

Low pin count DfT technique for RFID ICs (Abstract)

Marcelo de Souza Moraes , CEITEC S. A. Porto Alegre - RS - Brazil
Marcos Barcellos Herve , CEITEC S. A. Porto Alegre - RS - Brazil
Marcelo Soares Lubaszewski , CEITEC S. A. Porto Alegre - RS - Brazil
pp. 31-36

Generation and compaction of mixed broadside and skewed-load n-detection test sets for transition faults (Abstract)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
pp. 37-42

A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures (Abstract)

Ingrid Verbauwhede , KU Leuven, ESAT/SCD-COSIC and IBBT, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium
Bruno Rouzeyre , LIRMM (Université Montpellier II /CNRS UMR 5506), Montpellier, France
Mane-Lise Flottes , LIRMM (Université Montpellier II /CNRS UMR 5506), Montpellier, France
Giorgio Di Natale , LIRMM (Université Montpellier II /CNRS UMR 5506), Montpellier, France
Amitabh Das , KU Leuven, ESAT/SCD-COSIC and IBBT, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium
Jean Da Rolt , LIRMM (Université Montpellier II /CNRS UMR 5506), Montpellier, France
pp. 43-48

#SAT-based vulnerability analysis of security components — A case study (Abstract)

Bernd Becker , Albert-Ludwigs-University of Freiburg, Georges-Köhler-Allee 051, 79110 Freiburg, Germany
Ilia Polian , University of Passau, Innstrasse 43, 94032 Passau, Germany
Eberhard Bohl , Robert Bosch GmbH 72703 Reutlingen
Alexander Czutro , Albert-Ludwigs-University of Freiburg, Georges-Köhler-Allee 051, 79110 Freiburg, Germany
Tobias Schubert , Albert-Ludwigs-University of Freiburg, Georges-Köhler-Allee 051, 79110 Freiburg, Germany
Linus Feiten , Albert-Ludwigs-University of Freiburg, Georges-Köhler-Allee 051, 79110 Freiburg, Germany
Matthias Sauer , Albert-Ludwigs-University of Freiburg, Georges-Köhler-Allee 051, 79110 Freiburg, Germany
pp. 49-54

Software exploitable hardware Trojans in embedded processor (Abstract)

Swarup Bhunia , Case Western Reserve University, Cleveland, OH, USA - 44106
Seetharam Narasimhan , Case Western Reserve University, Cleveland, OH, USA - 44106
Aswin Krishna , Case Western Reserve University, Cleveland, OH, USA - 44106
Tatini Mal-Sarkar , Hathaway Brown High School, Cleveland, OH, USA - 44106
Xinmu Wang , Case Western Reserve University, Cleveland, OH, USA - 44106
pp. 55-58

Minimization of Trojan footprint by reducing Delay/Area impact (Abstract)

Elaheh Bozorgzadeh , Computer Science Department, University of California, Irvine, Irvine, USA
Ian G. Harris , Computer Science Department, University of California, Irvine, Irvine, USA
Mehryar Rahmatian , Computer Science Department, University of California, Irvine, Irvine, USA
Hessam Kooti , Computer Science Department, University of California, Irvine, Irvine, USA
pp. 59-62

Designing and implementing a Malicious 8051 processor (Abstract)

Juan Carlos Martinez Santos , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115
Yunsi Fei , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115
pp. 63-66

On the design of two single event tolerant slave latches for scan delay testing (Abstract)

Marco Ottavi , Department of Electronic Engineering, University of Rome “Tor Vergata”, Via del Politecnico 1, 00133, Rome, Italy
Salvatore Pontarelli , Department of Electronic Engineering, University of Rome “Tor Vergata”, Via del Politecnico 1, 00133, Rome, Italy
Yang Lu , Department of Electrical and Computer Engineering, Northeastern University, 360 Huntington Avenue, Boston, MA 02115 USA
Fabrizio Lombardi , Department of Electrical and Computer Engineering, Northeastern University, 360 Huntington Avenue, Boston, MA 02115 USA
pp. 67-72

Hardening a memory cell for low power operation by gate leakage reduction (Abstract)

Jie Han , University of Alberta, Dept of ECE, Edmonton, Canada
Fabrizio Lombardi , Northeastern University, Dept. of ECE Boston MA 02115, USA
Jianping Gong , Northeastern University, Dept. of ECE Boston MA 02115, USA
Yong-Bin Kim , Northeastern University, Dept. of ECE Boston MA 02115, USA
pp. 73-78

Single event upset tolerance in flip-flop based microprocessor cores (Abstract)

Adrian Evans , TIMA Laboratory, CNRS, 38031 Grenoble, France
Stefanos Valadimas , University of Athens, Dept. of Informatics and Telecommunications, 15784 Athens, Greece
Yiorgos Tsiatouhas , University of Ioannina, Dept. of Computer Science, 45110 Ioannina, Greece
Angela Arapoyanni , University of Athens, Dept. of Informatics and Telecommunications, 15784 Athens, Greece
pp. 79-84

An on-line soft error mitigation technique for control logic of VLIW processors (Abstract)

Alireza Rohani , Testable Design and Test of Integrated Systems Group CUT, University of Twente, Enschede, The Netherlands
Hans G. Kerkhoff , Testable Design and Test of Integrated Systems Group CUT, University of Twente, Enschede, The Netherlands
pp. 85-91

Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors (Abstract)

Jie Hu , Intel Corporation, Portland, OR 97124, USA
Shuai Wang , Department of Computer Science and Technology, Nanjing University, Nanjing, Jiang Su 210046, China
Chuanlei Zheng , Department of Computer Science and Technology, Nanjing University, Nanjing, Jiang Su 210046, China
Parijat Shukla , Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA
pp. 92-97

Amalgamated q-ary codes for multi-level flash memories (Abstract)

Yifat Manzor , Faculty of Engineering, Bar-Ilan University
Osnat Keren , Faculty of Engineering, Bar-Ilan University
pp. 98-103

Accurate calculation of SET propagation probability for hardening (Abstract)

Sreenivas Gangadhar , Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, IL 62901
Spyros Tragoudas , Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, IL 62901
pp. 104-108

Transient pulse propagation using the Weibull distribution function (Abstract)

Adam Watkins , Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, Illinois 62901
Spyros Tragoudas , Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, Illinois 62901
pp. 109-114

Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs (Abstract)

Luca Sterpone , Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy
Cinzia Bernardeschi , Department of Information Engineering, University of Pisa, Italy
Luca Cassano , Department of Information Engineering, University of Pisa, Italy
Andrea Domenici , Department of Information Engineering, University of Pisa, Italy
pp. 115-120

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies (Abstract)

D. Rossi , Università di Bologna, DEIS, Bologna - Italy
A. Paccagnella , Università di Padova, Dip. Ingegneria dell'Informazione, Padova - Italy
S. Gerardin , Università di Padova, Dip. Ingegneria dell'Informazione, Padova - Italy
M. Violante , Politecnico di Torino, Dip. Automatica e Informatica, Torino - Italy
L. Sterpone , Politecnico di Torino, Dip. Automatica e Informatica, Torino - Italy
M. Sonza Reorda , Politecnico di Torino, Dip. Automatica e Informatica, Torino - Italy
M. Omana , Università di Bologna, DEIS, Bologna - Italy
M. Bagatin , Università di Padova, Dip. Ingegneria dell'Informazione, Padova - Italy
C. Metra , Università di Bologna, DEIS, Bologna - Italy
A. Salsano , Università di Roma, “Tor Vergata”, Dip. Ingegneria Elettronica, Roma - Italy
S. Pontarelli , Università di Roma, “Tor Vergata”, Dip. Ingegneria Elettronica, Roma - Italy
M. Ottavi , Università di Roma, “Tor Vergata”, Dip. Ingegneria Elettronica, Roma - Italy
C. Bolchini , Politecnico di Milano, Dip. Elettronica e Informazione, Milano - Italy
A. Miele , Politecnico di Milano, Dip. Elettronica e Informazione, Milano - Italy
C. Sandionigi , Politecnico di Milano, Dip. Elettronica e Informazione, Milano - Italy
pp. 121-125

A systematic methodology to improve yield per area of highly-parallel CMPs (Abstract)

Da Cheng , University of Southern California
Sandeep K. Gupta , University of Southern California
pp. 126-133

On the multiple fault detection of a nano crossbar (Abstract)

T. Nandha Kumar , Department of Electrical and Electronic Engineering, The University of Nottingham, Malaysia
Fabrizio Lombardi , Dcpt of ECE, Northeastern University, Boston MA 02115
Nohpill Park , Dept of Comp. Science, Oklahoma State University, Stillwater, OK 74078
Haider A. F. Almurib , Department of Electrical and Electronic Engineering, The University of Nottingham, Malaysia
pp. 134-139

Prediction of gate delay variation for CNFET under CNT density variation (Abstract)

Ali Arabi M. Shahi , Department of Electrical & Computer Engineering, University of New Mexico Albuquerque, NM 87131, USA
Payman Zarkesh-Ha , Department of Electrical & Computer Engineering, University of New Mexico Albuquerque, NM 87131, USA
pp. 140-145

Built-in generation of multi-cycle broadside tests (Abstract)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
pp. 146-151

Fast single-FPGA fault injection platform (Abstract)

Gabriel L. Nazar , Institute de Informatica, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Luigi Carro , Institute de Informatica, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
pp. 152-157

Incorporating parameter variations in BTI impact on nano-scale logical gates analysis (Abstract)

Francky Catthoor , Kapeldreef 75, B-3001, Leuven, Belgium
Praveen Raghavan , Kapeldreef 75, B-3001, Leuven, Belgium
Halil Kukner , Kapeldreef 75, B-3001, Leuven, Belgium
Seyab Khan , Computer Engineering Laboratory, Delft University of Technology, Mekelweg 4, 2628 CD Delft, The Netherland
Said Hamdioui , Computer Engineering Laboratory, Delft University of Technology, Mekelweg 4, 2628 CD Delft, The Netherland
pp. 158-163

Relating digital imager defect rates to pixel size, sensor area and ISO (Abstract)

Zahava Koren , Dept. of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, 01003
Israel Koren , Dept. of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, 01003
Glenn H. Chapman , School of Engineering Science, Simon Fraser University, Burnaby, B. C., Canada, V5A 1S6
Rohit Thomas , School of Engineering Science, Simon Fraser University, Burnaby, B. C., Canada, V5A 1S6
pp. 164-169

A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience (Abstract)

Kyu-Nam Shim , Dept. of Electrical and Computer Engineering, Texas A&M University, College Station, TX 77843, USA
Jiang Hu , Dept. of Electrical and Computer Engineering, Texas A&M University, College Station, TX 77843, USA
pp. 170-177

Implementing defect tolerance in 3D-ICs by exploiting degrees of freedom in assembly (Abstract)

Asad Bawa , Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712-1084
Nur A. Touba , Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712-1084
M. Tauseef Rab , Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712-1084
pp. 178-181

Optimal choice of arithmetic compactors for mixed-signal systems (Abstract)

Vadim Geurkov , Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada
pp. 182-186

Dual-edge-triggered FF with timing error detection capability (Abstract)

Hideo Ito , Graduate School of Advanced Integration Science, Chiba University, 1-33 Yayoi-cho Inage-ku Chiba-shi, 263-8522, Japan
Kazuteru Namba , Graduate School of Advanced Integration Science, Chiba University, 1-33 Yayoi-cho Inage-ku Chiba-shi, 263-8522, Japan
Takashi Katagiri , Graduate School of Advanced Integration Science, Chiba University, 1-33 Yayoi-cho Inage-ku Chiba-shi, 263-8522, Japan
pp. 187-192

Improving small-delay fault coverage for on-chip delay measurement (Abstract)

Hideo Ito , Graduate School of Advanced Integration Science, Chiba University Chiba, Japan
Wenpo Zhang , Graduate School of Advanced Integration Science, Chiba University Chiba, Japan
Kazuteru Namba , Graduate School of Advanced Integration Science, Chiba University Chiba, Japan
pp. 193-198

Faults affecting the control blocks of PV arrays and techniques for their concurrent detection (Abstract)

D. Rossi , ARCES - DEIS, University of Bologna Bologna, Italy
pp. 199-204

Dirty data vulnerability mitigation by means of sharing management in cache coherence protocols (Abstract)

Mohammad Maghsoudloo , Department of Computer Engineering and Information Technology, Amirkabir University of Technology (Tehran Polytechnic)
Hamid R. Zarandi , Department of Computer Engineering and Information Technology, Amirkabir University of Technology (Tehran Polytechnic)
pp. 205-210

A mechanism to verify cache coherence transactions in multicore systems (Abstract)

Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst MA 01003, USA
Rance Rodrigues , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst MA 01003, USA
Israel Koren , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst MA 01003, USA
pp. 211-216

Dependable routing in multi-chip NoC platforms for automotive applications (Abstract)

Tomohiro Yoneda , National Institute of Informatics
Masashi Imai , Hirosaki University
pp. 217-224

Using the Berlekamp-Massey algorithm to obtain LFSR characteristic polynomials for TPG (Abstract)

Oscar Acevedo , ECE Department, Southern Illinois University, Carbondale, IL 62901-6603
Dimitri Kagaris , ECE Department, Southern Illinois University, Carbondale, IL 62901-6603
pp. 233-238

Maintaining proximity to functional operation conditions under enhanced-scan tests based on functional broadside tests (Abstract)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
pp. 239-244
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