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2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (2008)
Oct. 1, 2008 to Oct. 3, 2008
ISSN: 1550-5774
ISBN: 978-0-7695-3365-0
pp: 323-331
ABSTRACT
The tremendous increase in device density of present day designs is accompanied by a corresponding increase in transistor failures (hard faults), posing a major challenge to current fault tolerant techniques and tools. We propose a novel "design-time" fault-tolerance methodology at architecture/circuit levels to improve the reliability of applications, where it is possible to classify computations into two categories- (i) those which contribute to quality degradation and, (ii) those which result in total system failure. The proposed scheme enhances system reliability by making appropriate trade-offs between area, output quality (signal to noise ratio or mean square error), and fault tolerance. This low-overhead generic methodology is suitable not only for scaled CMOS technologies, but is also applicable to future nanotechnologies (carbon nanotubes etc.) as well, where such defects are expected to be prevalent. We evaluated this technique on a widely used DSP system – Finite Impulse Response (FIR) filters (where minor degradation in quality can be tolerated). Results show that our technique achieves an improvement between 73.4%-450% (in terms of total system failure probability under iso-redundancy) compared to conventional fault tolerance techniques.
INDEX TERMS
Fault Tolerance, Graceful degradation, DSP systems
CITATION

C. Augustine, K. Roy and N. Banerjee, "Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and its Application to Digital Signal Processing Systems," 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems(DFT), vol. 00, no. , pp. 323-331, 2008.
doi:10.1109/DFT.2008.43
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