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22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) (2007)
Rome, Italy
Sept. 26, 2007 to Sept. 28, 2007
ISBN: 0-7695-2885-6
TABLE OF CONTENTS
Introduction

Committees (PDF)

pp. xiii
Session 1 - Reliable NoCs and SoCs

Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code (Abstract)

Avijit Dutta , University of Texas, Austin, TX
Nur A. Touba , University of Texas, Austin, TX
pp. 3-11

Fault Tolerant Source Routing for Network-on-chip (Abstract)

Young Bok Kim , Northeastern University, Boston, MA
Yong-Bin Kim , Northeastern University, Boston, MA
pp. 12-20

Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model (Abstract)

Armin Alaghi , University of Tehran, 14399 Tehran, IRA
Naghmeh Karimi , University of Tehran, 14399 Tehran, IRA
Mahshid Sedghi , University of Tehran, 14399 Tehran, IRA
Zainalabedin Navabi , University of Tehran, 14399 Tehran, IRA
pp. 21-29

Fault Tolerant SoC Architecture Design for JPEG2000 using Partial Reconfigurability (Abstract)

Abderrahim Doumar , University of Technology of Troyes, France
Kentaroh Katoh , University of Technology of Troyes, France
Hideo Ito , University of Technology of Troyes, France
pp. 30-40
Session 2 - Single Event Effects

Estimating Error Propagation Probabilities with Bounded Variances (Abstract)

Hossein Asadi , Northeastern University Boston, MA
Mehdi B. Tahoori , Northeastern University Boston, MA
Chandra Tirumurti , Intel Corporation
pp. 41-49

Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture (Abstract)

Ravi Bonam , University of Missouri-Rolla, Rolla, MO 65409-0040, USA
Yong-Bin Kim , Northeastern University, Boston, MA 02115, USA
Minsu Choi , University of Missouri-Rolla, Rolla, MO 65409-0040, USA
pp. 161-169
Session 2 - Single Event Effects

SET Emulation Under a Quantized Delay Model (Abstract)

Mario García Valderas , Universidad Carlos III de Madrid
Raúl Fernández Cardenal , Universidad Carlos III de Madrid
Celia López Ongil , Universidad Carlos III de Madrid
Marta Portela García , Universidad Carlos III de Madrid
Luis Entrena , Universidad Carlos III de Madrid
pp. 68-78
Session 3 - Defect and Fault Tolerance

Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs (Abstract)

A. Manuzzato , Università di Padova
P. Rech , Università di Padova
S. Gerardin , Università di Padova
A. Paccagnella , Università di Padova
L. Sterpone , Politecnico di Torino
M. Violante , Politecnico di Torino
pp. 79-86

TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs (Abstract)

Cristiana Bolchini , Politecnico di Milano
Antonio Miele , Politecnico di Milano
Marco D. Santambrogio , Politecnico di Milano
pp. 87-95

Optimization of Self Checking FIR filters by means of Fault Injection Analysis (Abstract)

S. Pontarelli , University of Rome
L. Sterpone , Politecnico di Torino
G.C. Cardarilli , University of Rome
M. Re , University of Rome
M. Sonza Reorda , Politecnico di Torino
A. Salsano , University of Rome
M. Violante , Politecnico di Torino
pp. 96-104
Session 4 - Fault Injection and Reliability Analysis

Evaluation of Single Event Upset Mitigation Schemes for SRAM based FPGAs using the FLIPPER Fault Injection Platform (Abstract)

M. Alderighi , INAF, Istituto di Astrofisica Spaziale e Fisica Cosmica, Milano, ITALY
F. Casini , Sanitas EG s.r.l., Milano, ITALY
S. D'Angelo , INAF, Istituto di Astrofisica Spaziale e Fisica Cosmica, Milano, ITALY
S. Pastore , Sanitas EG s.r.l., Milano, ITALY
G.R. Sechi , INAF, Istituto di Astrofisica Spaziale e Fisica Cosmica, Milano, ITALY
R. Weigand , ESA/ESTEC, European Space Agency, Noordwijk, THE NETHERLANDS
pp. 105-113

A Functional Verification based Fault Injection Environment (Abstract)

A. Benso , Politecnico di Torino, Italy
A. Bosio , Politecnico di Torino, Italy
S. Di Carlo , Politecnico di Torino, Italy
R. Mariani , Yogitech S.p.A, San Martino Ulmiano Pisa, Italy
pp. 114-122

Comparing fail-safe microcontroller architectures in light of IEC 61508 (Abstract)

Riccardo Mariani , YOGITECH SpA
Peter Fuhrmann , Philips Research Europe, Germany
pp. 123-131

A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip (Abstract)

G. Beltrame , European Space Agency
C. Bolchini , Politecnico di Milano, Italy
L. Fossati , Politecnico di Milano, Italy
A. Miele , Politecnico di Milano, Italy
D. Sciuto , Politecnico di Milano, Italy
pp. 132-142
Interactive Poster Session

A Defect-Tolerant Molecular-Based Memory Architecture (Abstract)

Yoon-Hwa Choi , Hongik University, Seoul, Korea
Myeong-Hyeon Lee , Hongik University, Seoul, Korea
pp. 143-151

Checker Design for On-line Testing of Xilinx FPGA Communication Protocols (Abstract)

Martin Straka , Brno University of Technology
Jiri Tobola , Brno University of Technology
Zdenek Kotasek , Brno University of Technology
pp. 152-160

Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture (Abstract)

Ravi Bonam , University of Missouri-Rolla, Rolla, MO 65409-0040, USA
Yong-Bin Kim , Northeastern University, Boston, MA 02115, USA
Minsu Choi , University of Missouri-Rolla, Rolla, MO 65409-0040, USA
pp. 161-169

Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs (Abstract)

Mehdi Kamal , Sharif University of Technology
Somayyeh Koohi , Sharif University of Technology
Shaahin Hessabi , Sharif University of Technology
pp. 179-187

Production Yield and Self-Configuration in the Future Massively Defective Nanochips (Abstract)

Piotr Zajac , University of Toulouse, France
Jacques Henri Collet , University of Toulouse, France
pp. 197-205

Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs (Abstract)

A. Matrosova , Tomsk State University, RUSSIA
E. Loukovnikova , Tomsk State University, RUSSIA
S. Ostanin , Tomsk State University, RUSSIA
A. Zinchuck , Tomsk State University, RUSSIA
E. Nikolaeva , Tomsk State University, RUSSIA
pp. 206-214

Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Desig (Abstract)

Waleed K. Al-Assadi , University of Missouri - Rolla
Sindhu Kakarla , University of Missouri - Rolla
pp. 215-222

Timing-Aware Diagnosis for Small Delay Defects (Abstract)

Takashi Aikyo , Semiconductor Technology Academic Research Center
Hiroshi Takahashi , Ehime University
Yoshinobu Higami , Ehime University
Junichi Ootsu , Ehime University
pp. 223-234
Session 5 - Testing and Design for Testability

A-Diagnosis: A Complement to Z-Diagnosis (Abstract)

Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
pp. 235-242

Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines (Abstract)

Hiroshi Takahashi , Ehime University
Yoshinobu Higami , Ehime University
Toru Kikkawa , Ehime University
Takashi Aikyo , Ehime University
Yuzo Takamatsu , Ehime University
Koji Yamazaki , Meiji University
Toshiyuki Tsutsumi , Meiji University
Hiroyuki Yotsuyanagi , University of Tokushima
Masaki Hashizume , University of Tokushima
pp. 243-251

Analysis of Specified Bit Handling Capability of Combinational Expander Networks (Abstract)

Abhijit Jas , Advanced Test Technology, Intel Corporation
Srinivas Patil , Advanced Test Technology, Intel Corporation
pp. 252-260

Reduction of Fault Latency in Sequential Circuits by using Decomposition (Abstract)

Ilya Levin , Tel Aviv University, Israel
Benjamin Abramov , Tel Aviv University, Israel
Vladimir Ostrovsky , Tel Aviv University, Israel
pp. 261-272
Session 6 - Soft Errors

Soft Error Hardening for Asynchronous Circuits (Abstract)

Weidong Kuang , University of Texas Pan American, Edinburg
Casto Manuel Ibarra , University of Texas Pan American, Edinburg
Peiyi Zhao , Chapman University, Orange, CA
pp. 273-281

Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing (Abstract)

Takashi IKEDA , Chiba University
Kazuteru NAMBA , Chiba University
Hideo ITO , Chiba University
pp. 282-290

An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains (Abstract)

J. Lagos-Benites , Pontificia Universidad Católica del Perú, Lima, Perú
D. Appello , STMicroelectronics, Milano, Italy
P. Bernardi , Politecnico di Torino, Torino, Italy
M. Grosso , Politecnico di Torino, Torino, Italy
D. Ravotto , Politecnico di Torino, Torino, Italy
E. Sánchez , Politecnico di Torino, Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Torino, Italy
pp. 291-302
Session 7 - Defect and Fault Tolerance

Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations (Abstract)

J. Semião , Univ. of Algarve, Portugal
J. J. Rodríguez-Andina , Univ. of Vigo, Spain
F. Vargas , PUCRS, Brazil
M. B. Santos , IST / INESC-ID, Portugal
I. C. Teixeira , IST / INESC-ID, Portugal
J. P. Teixeira , IST / INESC-ID, Portugal
pp. 303-311

RAM-based fault tolerant state machines for FPGAs (Abstract)

Laura Frigerio , Politecnico di Milano, Dip. di Elettronica e Informazione
Fabio Salice , Politecnico di Milano, Dip. di Elettronica e Informazione
pp. 312-320

Spare Parts in Analog Circuits: a Filter Example (Abstract)

Erik Schuler , Universidade Federal do Rio Grande do Sul
Adão Júnior Antônio de Souza , Universidade Federal do Rio Grande do Sul
Luigi Carro , Universidade Federal do Rio Grande do Sul
pp. 321-330
Session 8 - Dependable Solutions for Memories and Storage

Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories (Abstract)

Costas Argyrides , University of Bristol, UK
Hamid R. Zarandi , Amirkabir University of Technology, Tehran, IRAN
Dhiraj K. Pradhan , University of Bristol, UK
pp. 340-348
Session 9 - Reliable Design Techniques

Lazy Error Detection for Microprocessor Functional Units (Abstract)

Mahmut Yilmaz , Duke University
Albert Meixner , Duke University
Sule Ozev , Duke University
Daniel J. Sorin , Duke University
pp. 361-369

Effective Checkpoint and Rollback Using Hardware/OS Collaboration (Abstract)

Portolan Michele , TIMA Laboratory (CNRS, InPG, UJF), France
Leveugle Régis , TIMA Laboratory (CNRS, InPG, UJF), France
pp. 370-378

On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors (Abstract)

G. Xenoulis , University of Piraeus, Greece
M. Psarakis , University of Piraeus, Greece
D. Gizopoulos , University of Piraeus, Greece
A. Paschalis , University of Athens, Greece
pp. 379-397
Session 10 - Emerging Technologies - 1

A Scalable Framework for Defect Isolation of DNA Self-assemlbled Networks (Abstract)

Masura Fakushi , Tohuko University
Susumo Horiguchi , Tohuko University
Luke Demoracski , Northeastern University
Fabrizio Lombardi , Northeastern University
pp. 391-399

Error Tolerance of DNA Self-Healing Assemblies by Puncturing (Abstract)

Masoud Hashempour , Northeastern University, Dept. of ECE, Boston MA
Zahra Mashreghian Arani , Northeastern University, Dept. of ECE, Boston MA
Fabrizio Lombardi , Northeastern University, Dept. of ECE, Boston MA
pp. 400-408

Fault Secure Encoder and Decoder for Memory Applications (Abstract)

Helia Naeimi , California Institute of Technology
Andre DeHon , University of Pennsylvania
pp. 409-417

Safety Evaluation of NanoFabrics (Abstract)

Michelangelo Grosso , Politecnico di Torino, Torino, Italy
Maurizio Rebaudengo , Politecnico di Torino, Torino, Italy
Matteo Sonza Reorda , Politecnico di Torino, Torino, Italy
pp. 418-426

Nanofabric PLA architecture with Redundancy Enhancement (Abstract)

Mandar V. Joshi , University of Missouri-Rolla
Waleed K. Al-Assadi , University of Missouri-Rolla
pp. 427-438
Session 11 - Testing

High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations (Abstract)

Michele Favalli , University of Ferrara, Italy
Marcello Dalpasso , University of Ferrara, Italy
pp. 448-456
Session 12 - Emerging Technologies - 2

Testing Reversible One-Dimensional QCA Arrays for Multiple F (Abstract)

J. Huang , Northeastern University, Boston, MA
X. Ma , Northeastern University, Boston, MA
C. Metra , University of Bologna, Bologna, Italy
F. Lombardi , Northeastern University, Boston, MA
pp. 469-477

Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder (Abstract)

Timothy J. Dysart , University of Notre Dame
Peter M. Kogge , University of Notre Dame
pp. 478-486

On the Error Effects of Random Clock Shifts in Quantum-dot Cellular Automata Circuits (Abstract)

M. Ottavi , Northeastern University
H. Hashempour , Northeastern University
V. Vankamamidi , Northeastern University
F. Karim , University of British Columbia
K. Walus , University of British Columbia
A. Ivanov , University of British Columbia
pp. 487-498
Session 13 - Reliable Applications

Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections (Abstract)

P. Maistri , TIMA Laboratory - 46 Avenue Félix Viallet - 38031 Grenoble Cedex - FRANCE
P. Vanhauwaert , TIMA Laboratory - 46 Avenue Félix Viallet - 38031 Grenoble Cedex - FRANCE
R. Leveugle , TIMA Laboratory - 46 Avenue Félix Viallet - 38031 Grenoble Cedex - FRANCE
pp. 499-507

Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits (Abstract)

Francesco Regazzoni , University of Lugano, Lugano, Switzerland
Thomas Eisenbarth , Horst Gortz Institute for IT Security, RUB, Bochum, Germany
Johann Großschädl , University of Bristol, Bristol, UK
Luca Breveglieri , Politecnico di Milano, Milano, Italy
Paolo Ienne , EPFL, Lausanne, Switzerland.
Israel Koren , University of Massachusetts
Christof Paar , Horst Gortz Institute for IT Security, RUB, Bochum, Germany
pp. 508-516

A Fault-Tolerant Active Pixel Sensor to Correct In-Field Hot-Pixel Defects (Abstract)

Jozsef Dudas , Simon Fraser University
Michelle L. La Haye , Simon Fraser University
Jenny Leung , Simon Fraser University
Glenn H. Chapman , Simon Fraser University
pp. 517-525

Quantitative Analysis of In-Field Defects in Image Sensor Arrays (Abstract)

Jenny Leung , Simon Fraser University
Jozsef Dudas , Simon Fraser University
Glenn H. Chapman , Simon Fraser University
Israel Koren , University of Massachusetts
Zahava Koren , University of Massachusetts
pp. 526-534
Author Index

Author Index (PDF)

pp. 535
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