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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2006)
Arlington, Virginia, USA
Oct. 4, 2006 to Oct. 6, 2006
ISSN: 1550-5774
ISBN: 0-7695-2706-X
TABLE OF CONTENTS
Introduction
Invited Talk
Session 1: Adaptive Design and Gate Level Redundancy

Adaptive Design for Performance-Optimized Robustness (Abstract)

Kevin Nowka , IBM Austin Research Laboratory, USA
Abdulkadir Utku Diril , Nvidia Corporation
Abhijit Chatterjee , Georgia Institute of Technology, USA
Ramyanshu Datta , The University of Texas at Austin, USA
Jacob A. Abraham , The University of Texas at Austin, USA
pp. 3-11

Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration (Abstract)

Stephen Wyatt , IBM Microelectronics Division, USA
Tian Xia , University of Vermont, USA
Rupert Ho , IBM Microelectronics Division, USA
pp. 12-19

Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates (Abstract)

Kristian Granhaug , University of Oslo, Norway
Snorre Aunet , University of Oslo, Norway
pp. 20-28

Gate Failures Effectively Shape Multiplexing (Abstract)

W. Ibrahim , United Arab Emirates University, United Arab Emirates
Y.A. Alkhawwar , United Arab Emirates University, United Arab Emirates
M.H. Sulieman , United Arab Emirates University, United Arab Emirates
V. Beiu , United Arab Emirates University, United Arab Emirates
pp. 29-40
Session 2: Delay Test

Test Generation for Open Defects in CMOS Circuits (Abstract)

I. Pomeranz , Purdue University, USA
N. Devtaprasanna , University of Iowa, USA
S. M. Reddy , University of Iowa, USA
A. Gunda , LSI Logic Corp., USA
P. Krishnamurthy , LSI Logic Corp., USA
pp. 41-49

Implicit Critical PDF Test Generation with Maximal Test Efficiency (Abstract)

Maria K. Michael , University of Cyprus, Cyprus
Kyriakos Christou , University of Cyprus, Cyprus
Spyros Tragoudas , Southern Illinois University, USA
pp. 50-58

Selecting High-Quality Delay Tests for Manufacturing Test and Debug (Abstract)

Srinivas Patil , Intel Corporation, USA
Suriyaprakash Natarajan , Intel Corporation, USA
Hangkyu Lee , Purdue University, USA
Irith Pomeranz , Purdue University, USA
pp. 59-70
Session 3: Emerging Technologies

Testing Reversible 1D Arrays for Molecular QCA (Abstract)

C. Metra , University of Bologna, Italy
F. Lombardi , Northeastern University, USA
J. Huang , Northeastern University, USA
X. Ma , Northeastern University, USA
pp. 71-79

Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design (Abstract)

Nohpill Park , Oklahoma State University, USA
Myungsu Choi , Oklahoma State University, USA
Zachary Patitz , Oklahoma State University, USA
Minsu Choi , University of Missouri-Rolla, USA
pp. 80-88

Error Tolerance of DNA Self-Assembly by Monomer Concentration Control (Abstract)

Fabrizio Lombardi , Northeastern University, USA
Yong-Bin Kim , Northeastern University, USA
Byunghyun Jang , Northeastern University, USA
pp. 89-97

Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects (Abstract)

Yong-Bin Kim , Northeastern University, USA
Yadunandana Yellambalase , University of Missouri-Rolla, USA
Minsu Choi , University of Missouri-Rolla, USA
pp. 98-106

A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices (Abstract)

Reza M.P. Rad , University of Maryland Baltimore County, USA
Mohammad Tehranipoor , University of Maryland Baltimore County, USA
pp. 107-118
Session 4: Test Compression

Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor (Abstract)

Sverre Wichlund , Nordic Semiconductor, Norway
Frank Berntsen , Nordic Semiconductor, Norway
Einar J. Aas , Norwegian University of Science and Technology, Norway
pp. 119-127

A Novel Methodology for Functional Test Data Compression (Abstract)

Hamidreza Hashempour , Northeastern University, USA
Fabrizio Lombardi , Northeastern University, USA
pp. 128-135

Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters (Abstract)

Toshinori Takabatake , Shonan Institute of Technology, Japan
Masao Yanagisawa , Waseda University, Japan
Youhua Shi , Waseda University, Japan
Gang Zeng , Nagoya University, Japan
Hideo Ito , Chiba University, Japan
pp. 136-144

An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint (Abstract)

B. F. Womack , University of Texas at Austin, USA
Geewhun Seok , University of Texas at Austin, USA
Tony Ambler , University of Texas at Austin, USA
Il-Soo Lee , University of Texas at Austin, USA
pp. 145-156
Invited Talk
Session 5: Defect Tolerance and Error Correction

Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC (Abstract)

Vijay Jain , University of South Florida, USA
Glenn H. Chapman , Simon Fraser University, Canada
pp. 157-165

Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost (Abstract)

Akhil Garg , STMicroelectronics India Pvt. Ltd., India
Prashant Dubey , STMicroelectronics India Pvt. Ltd., India
pp. 166-174

Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems (Abstract)

Haruhiko Kaneko , Japan Aerospace Exploration Agency, Japan
Eiji Fujiwara , Tokyo Institute of Technology, Japan
Hiroyuki Ohde , Tokyo Institute of Technology, Japan
pp. 175-183

Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique (Abstract)

Chen Wei , National University of Defense Technology, P.R. China
Wang Zhiying , National University of Defense Technology, P.R. China
Dai Kui , National University of Defense Technology, P.R. China
Liu Fang , National University of Defense Technology, P.R. China
Gong Rui , National University of Defense Technology, P.R. China
pp. 184-196
Session 6: BIST and Pseudo-Functional Test

Low Power SoC Memory BIST (Abstract)

Andre Ivanov , Univ. of British Columbia, Canada
Yuejian Wu , Nortel, Canada
pp. 197-205

Synthesis of Efficient Linear Test Pattern Generators (Abstract)

Avijit Dutta , University of Texas, USA
Nur A. Touba , University of Texas, USA
pp. 206-214

An Approach to Minimizing Functional Constraints (Abstract)

Sreejit Chakravarty , Intel Corporation
Abhijit Jas , Intel Corporation
Yi-Shing Chang , Intel Corporation
pp. 215-226
Session 7: Reliability Evaluation and Analysis

Reliability Evaluation of Repairable/Reconfigurable FPGAs (Abstract)

F. Lombardi , Northeastern University, USA
V. Vankamamidi , Northeastern University, USA
M. Ottavi , Northeastern University, USA
S. Pontarelli , Universita di Roma "Tor Vergata", Italy
A. Salsano , Universita di Roma "Tor Vergata", Italy
pp. 227-235

Reliability Analysis of Self-Repairable MEMS Accelerometer (Abstract)

Wen-Ben Jone , University of Cincinnati, USA
Yu-Liang Wu , The Chinese University of Hong Kong, Hong Kong
Xingguo Xiong , University of Bridgeport, USA
pp. 236-244

Timing Failure Analysis of Commercial CPUs Under Operating Stress (Abstract)

Sanghoan Chang , Texas A&M University, USA
Gwan Choi , Texas A&M University, USA
pp. 245-253

Real Time Fault Injection Using Enhanced OCD -- A Performance Analysis (Abstract)

Andr? V. Fidalgo , Instituto Superior de Engenharia do Porto, Portugal
Gustavo R. Alves , Instituto Superior de Engenharia do Porto, Portugal
Jos? M. Ferreira , Faculdade de Engenharia da Universidade do Porto, Portugal
pp. 254-264
Session 8: Approaches for Soft Errors

Combined software and hardware techniques for the design of reliable IP processors (Abstract)

C. Bolchini , Politecnico di Milano, Italy
D. Sciuto , Politecnico di Milano, Italy
A. Miele , Politecnico di Milano, Italy
M. Violante , Politecnico di Torino, Italy
M. Rebaudengo , Politecnico di Torino, Italy
L. Sterpone , Politecnico di Torino, Italy
pp. 265-273

Low-Cost Hardening of Image Processing Applications Against Soft Errors (Abstract)

Hideo Fujiwara2 , Nara Institute of Science and Technology, Japan
Ilia Polian , Albert-Ludwigs-University, Germany
Bernd Becker , Albert-Ludwigs-University, Germany
Masato Nakasato , Nara Institute of Science and Technology, Japan
Satoshi Ohtake , Nara Institute of Science and Technology, Japan
pp. 274-279

Online hardening of programs against SEUs and SETs (Abstract)

M. Violante , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
C. A. L. Lisb? , Univ. Fed. do Rio Grande do Sul, Brazil
L. Carro , Univ. Fed. do Rio Grande do Sul, Brazil
pp. 280-290
Session 9: Interactive Papers

Equivalent IDDQ Tests for Systems with Regulated Power Supply (Abstract)

Chuen-Song Chen , University of Rhode Island, USA
Jien-Chung Lo , University of Rhode Island, USA
Tian Xia , University of Vermont, USA
pp. 291-299

Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead (Abstract)

Zdenek Pl?va , Technical University Liberec, Czech Republic
Jiri Jenicek , Technical University Liberec, Czech Republic
Zbynek Mader , Technical University Liberec, Czech Republic
Michal Jarkovsk? , Technical University Liberec, Czech Republic
Ondrej Nov? , Czech Technical University in Prague, Czech Repub
pp. 300-308

Bilateral Testing of Nano-scale Fault-tolerant Circuits (PDF)

Lei Fang , Virginia Tech, USA
Michael S. Hsiao , Virginia Tech, USA
pp. 309-317

A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates (Abstract)

Manoj Kumar Goparaju , Southern Illinois University Carbondale, USA
Spyros Tragoudas , Southern Illinois University Carbondale, USA
Sandeep Dechu , Southern Illinois University Carbondale, USA
pp. 318-326

Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit (Abstract)

Kazuteru Namba , Chiba University, Japan
Hideo Ito , Chiba University, Japan
Yoichi Sasaki , Chiba University, Japan
pp. 327-335

Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects (Abstract)

Walter Anheier , University of Bremen, Germany
Kishore K. Duganapalli , University of Bremen, Germany
Ajoy K. Palit , University of Bremen, Germany
pp. 336-344

SET Fault Tolerant Combinational Circuits Based on Majority Logic (Abstract)

L. Petroli , UFRGS, Brazil
L. Carro , UFRGS, Brazil
F. Kastensmidt , UFRGS, Brazil
C.A.L. Lisb? , UFRGS, Brazil
?. Michels , UFRGS, Brazil
pp. 345-352

An Improved Reconfiguration Method for Degradable Processor Arrays Using Genetic Algorithm (Abstract)

Yusuke Fukushima , Tohoku University, Japan
Masaru Fukushi , Tohoku University, Japan
Susumu Horiguchi , Tohoku University, Japan
pp. 353-361

A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy (Abstract)

Jin-Fu Li , National Central University, Taiwan
Yu-Jen Huang , National Central University, Taiwan
Da-Ming Chang , National Central University, Taiwan
pp. 362-370

Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers (Abstract)

S. Pontarelli , Universit? di Roma "Tor Vergata", Italy
A. Leandri , Universit? di Roma "Tor Vergata", Italy
M. Ottavi , Northeastern University Boston, USA
A. Salsano , Universit? di Roma "Tor Vergata", Italy
pp. 371-379

Recovery Mechanisms for Dual Core Architectures (Abstract)

Andreas Steininger , Vienna University of Technology, Austria
Christian El Salloum , Vienna University of Technology, Austria
Peter Tummeltshammer , Vienna University of Technology, Austria
Werner Harter , Robert Bosch GmbH, Germany
pp. 380-388

A Software-Based Error Detection Technique Using Encoded Signatures (Abstract)

Seyed Ghassem Miremadi , Sharif University of Technology, Iran
Mahdi Fazeli , Sharif University of Technology, Iran
Yasser Sedaghat , Sharif University of Technology, Iran
pp. 389-400
Session 10: Diagnosis

Effective Post-BIST Fault Diagnosis for Multiple Faults (Abstract)

Hiroshi Takahashi , Ehime University, Japan
Takashi Aikyo , Semiconductor Technology Academic Research Center (STARC)
Koji Yamazaki , Meiji University, Japan
Yuzo Takamatsu , Ehime University, Japan
Shuhei Kadoyama , Ehime University, Japan
Yasuo Sato , Semiconductor Technology Academic Research Center (STARC)
Yoshinobu Higami , Ehime University, Japan
pp. 401-109

Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics (Abstract)

Yukiya Miura , Tokyo Metropolitan University, Japan
Jiro Kato , Tokyo Metropolitan University, Japan
pp. 410-418

Scan-Based Delay Fault Tests for Diagnosis of Transition Faults (Abstract)

Sudhakar M. Reddy , University of Iowa, USA
Irith Pomeranz , Purdue University, USA
pp. 419-427

Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method (Abstract)

Jing-Jia Liou , National Tsing Hua University, Taiwan
Ying-Yen Chen , National Tsing Hua University, Taiwan
pp. 428-438
Session 11: Defect and Fault Tolerance in Sensors and NOCs

On-Line Mapping of In-Field Defects in Image Sensor Arrays (Abstract)

Cory Jung , Simon Fraser University, Canada
Jozsef Dudas , Simon Fraser University, Canada
Linda Wu , Simon Fraser University, Canada
Zahava Koren , University of Massachusetts, USA
Israel Koren , University of Massachusetts, USA
Glenn H. Chapman , Simon Fraser University, Canada
pp. 439-447

Fault Tolerant Active Pixel Sensors in 0.18 and 0.35 Micron Technologies (Abstract)

Glenn H. Chapman , Simon Fraser University, Canada
Jozsef Dudas , Simon Fraser University, Canada
Michelle L. La Haye , Simon Fraser University, Canada
Cory Jung , Simon Fraser University, Canada
David Chen , Simon Fraser University, Canada
pp. 448-456

NoC Interconnect Yield Improvement Using Crosspoint Redundancy (Abstract)

Cristian Grecu , University of British Columbia, Canada
Partha Pratim Pande , Washington State University, USA
Res Saleh , University of British Columbia, Canada
Andr? Ivanov , University of British Columbia, Canada
pp. 457-465

Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding (Abstract)

Benjamin Belzer , Washington State University, USA
Amlan Ganguly , Washington State University, USA
Cristian Grecu , University of British Columbia, Canada
Brett Feero , Washington State University, USA
Partha Pratim Pande , Washington State University, USA
pp. 466-476
Session 12: Test Techniques

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving (Abstract)

Paul Rosinger , University of Southampton, UK
Petru Eles , Link?ping University, Sweden
Zhiyuan He , Link?ping University, Sweden
Zebo Peng , Link?ping University, Sweden
Bashir M. Al-Hashimi , University of Southampton, UK
pp. 477-485

Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations (Abstract)

Fabrizio Lombardi , Northeastern University, USA
Fengming Zhang , LTX Corporation, USA
Peter Reiter , LTX Corporation, USA
Yong-Bin Kim , Northeastern University, USA
Warren Necoechea , LTX Corporation, USA
pp. 486-494

Multi-Site and Multi-Probe Substrate Testing on an ATE (Abstract)

Xiaojun Ma , Northeastern University, USA
Fabrizio Lombardi , Northeastern University, USA
pp. 495-506
Session 13: Processor Checking and Jitter

Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream (Abstract)

Shantanu Dutt , University of Illinois-Chicago, USA
Federico Rota , University of Illinois-Chicago, USA
Sahithi Krishna , University of Illinois-Chicago, USA
pp. 507-515

The Filter Checker: An Active Verification Management Approach (Abstract)

Joonhyuk Yoo , University of Maryland at College Park, USA
Manoj Franklin , University of Maryland at College Park, USA
pp. 516-524

Effect of Process Variation on the Performance of Phase Frequency Detector (Abstract)

Nandakumar P. Venugopal , University at Buffalo, The State University of New York, USA
Shambhu J. Upadhyaya , University at Buffalo, The State University of New York, USA
Nihal Shastry , University at Buffalo, The State University of New York, USA
pp. 525-534

Data Dependent Jitter Characterization Based on Fourier Analysis (Abstract)

Hao Zheng , Univerisity of South Florida, USA
Di Mu , University of Vermont, USA
Tian Xia , University of Vermont, USA
pp. 534-544
Session 14: Fault Tolerance Designs

A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells (Abstract)

Ramalingam Sridhar , State University of New York at Buffalo, USA
Lushan Liu, , State University of New York at Buffalo, USA
Shambhu Upadhyaya , State University of New York at Buffalo, USA
pp. 545-553

A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network (Abstract)

Takurou Murata , Polytechnic University
Itsuo Takanami , Polytechnic University
Tadayoshi Horita , Polytechnic University
pp. 554-562

VLSI Implementation of a Fault-Tolerant Distributed Clock Generation (Abstract)

A. Steininger , TU Vienna, Austria
G. Kempf , Austrian Aerospace GmbH, Austria
M. Ferringer , TU Vienna, Austria
G. Fuchs , TU Vienna, Austria
pp. 563-571

Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard (Abstract)

Arash Reyhani-Masoleh , University of Western Ontario, Canada
Mehran Mozaffari Kermani , University of Western Ontario, Canada
pp. 572-580
Author Index

Author Index (PDF)

pp. 581-583
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