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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2005)
Monterey, California
Oct. 3, 2005 to Oct. 5, 2005
ISBN: 0-7695-2464-8
TABLE OF CONTENTS
Cover
Introduction

Committees (PDF)

pp. xii
Yield Analysis and Modeling

Defects, Yield, and Design in Sublithographic Nano-electronics (Abstract)

Mehdi B. Tahoori , Northeastern University, Boston, MA
pp. 3-11

An ILP Formulation for Yield-driven Architectural Synthesis (Abstract)

Maciej Ciesielski , University of Massachusetts
Israel Koren , University of Massachusetts
Zhaojun Wo , University of Massachusetts
pp. 12-20

Design and Analysis of Self-Repairable MEMS Accelerometer (Abstract)

Yu-Liang Wu , Chinese University of Hong Kong
Xingguo Xiong , Chinese University of Hong Kong
Wen-Ben Jone , Chinese University of Hong Kong
pp. 21-32
Scan Design and Test Data Compression

Low Power BIST Based on Scan Partitioning (Abstract)

Jinkyu Lee , University of Texas, Austin
Nur A. Touba , University of Texas, Austin
pp. 33-41

Using Statistical Transformations to Improve Compression for Linear Decompressors (Abstract)

Samuel I. Ward , IBM Systems andTechnology Group
Chris Schattauer , University of Texas, Austin
Nur A. Touba , University of Texas, Austin
pp. 42-50

Securing Scan Design Using Lock and Key Technique (Abstract)

Chintan Patel , University of Maryland Baltimore County
Mohammed Tehranipoor , University of Maryland Baltimore County
Jeremy Lee , University of Maryland Baltimore County
Jim Plusquellic , University of Maryland Baltimore County
pp. 51-62
Reconfiguration

A Genetic Approach for the Reconfiguration of Degradable Processor Arrays (Abstract)

Susumu Horiguchi , Tohoku University
Yusuke Fukushima , Tohoku University
Masaru Fukushi , Tohoku University
pp. 63-71

Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard (Abstract)

L. Breveglieri , Politecnico di Milano, Milano, ITALY
P. Maistri , Politecnico di Milano, Milano, ITALY
I. Koren , University of Massachusetts, Amherst
pp. 72-80

An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement (Abstract)

Chin-Lung Su , National Tsing Hua University
Yi-Ting Yeh , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
pp. 81-92
Error Correcting Codes and Circuits

A Self Checking Reed Solomon Encoder: Design and Analysis (Abstract)

M. Re , University of Rome
S. Pontarelli , University of Rome
G.C. Cardarilli , University of Rome
A. Salsano , University of Rome
pp. 111-119

Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes (Abstract)

Yu-Lun Wan , University of Rhode Island
Eiji Fujiwara , Tokyo Institute of Technology
Jien-Chung Lo , University of Rhode Island
pp. 120-130
Fault Detection and Tolerance for Sensor and Flash Memory

Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring (Abstract)

D. N? , ST-Microelectronics ZI de Rousset BP 2
B. Saillet , IMT - Technop?le de Ch?teau Gombert
J.M. Portal , IMT - Technop?le de Ch?teau Gombert
pp. 131-139

Noise Analysis of Fault Tolerant Active Pixel Sensors (Abstract)

Cory Jung , Simon Fraser University,
Michelle L. La Haye , Simon Fraser University
Mohammad H. Izadi , Simon Fraser University
pp. 140-148

On-Line Identification of Faults in Fault-Tolerant Imagers (Abstract)

Israel Koren , University of Massachusetts, Amherst
Glenn H. Chapman , Simon Fraser University
Zahava Koren , University of Massachusetts, Amherst
Cory Jung , Simon Fraser University
Jozsef Dudas , Simon Fraser University
pp. 149-157

Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems (Abstract)

Shekhar Bhansal , University of South Florida, Tampa
Vijay Jain , University of South Florida, Tampa
Glenn H. Chapman , Simon Fraser University
pp. 158-168
Invited Talks
Delay Fault Test and Timing Consideration

The Other Side of the Timing Equation: a Result of Clock Faults (Abstract)

TM Mak , DEIS Univ. of Bologna
J. M. Cazeaux , DEIS Univ. of Bologna
M. Oma? , DEIS Univ. of Bologna
C. Metra , DEIS Univ. of Bologna
D. Rossi , DEIS Univ. of Bologna
pp. 169-177

A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits (Abstract)

Lei Wu , Texas A&M University
D. M. H. Walker , Texas A&M University
pp. 178-186

Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique (Abstract)

Mohammad Tehranipoor , Univ. of Maryland Baltimore
Nisar Ahmed , ASIC Product Development Center, Texas Instruments India
pp. 187-198
Defect and Fault Tolerant Design in QCA Circuits

Defect Characterization and Tolerance of QCA Sequential Devices and Circuits (Abstract)

M. Momenzadeh , Northeastern University
J. Huang , Northeastern University
F. Lombardi , Northeastern University
pp. 199-207

Modeling QCA Defects at Molecular-level in Combinational Circuits (Abstract)

Marco Ottavi , Northeastern University, Boston
Mariam Momenzadeh , Northeastern University, Boston
Fabrizio Lombardi , Northeastern University, Boston
pp. 208-216

QCA-Based Majority Gate Design under Radius of Effect-Induced Faults (Abstract)

Minsu Choi , University of Missouri-Rolla
Fred J. Meyer , Wichita State University, Kansas
Zachary D. Patitz , Oklahoma State University
Nohpill Park , Oklahoma State University
pp. 217-228
Interconnect Test

A Novel Pulse Echo Correlation Tool for Transmission Path Testing and Fault Finding using Pseudorandom Binary Sequences (Abstract)

Richard A. Guinee , Cork Institute of Technology, Cork, IRELAND
David M. Horan , Cork Institute of Technology, Cork, IRELAND
pp. 229-237

Methodologies and Algorithms for Testing Switch-Based NoC Interconnects (Abstract)

Cristian Grecu , University of British Columbia
Andr? Ivanov , University of British Columbia
Partha Pande , University of British Columbia
Res Saleh , University of British Columbia
Baosheng Wang , University of British Columbia
pp. 238-246

Test of Interconnection Opens Considering Coupling Signals (Abstract)

Roberto Gomez , National Institute for Astrophysics, Optics and Electronics - INAOE
Victor Champac , National Institute for Astrophysics, Optics and Electronics - INAOE
Alejandro Giron , National Institute for Astrophysics, Optics and Electronics - INAOE
pp. 247-258
Case Studies and Applications

FPGA oriented design of parity sharing RS codecs (Abstract)

M. Re , University of Rome
S. Pontarelli , University of Rome
A. Salsano , University of Rome
G.C. Cardarilli , University of Rome
pp. 259-265

A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems (Abstract)

Mahdi Fazeli , Sharif University of Technology
Seyed Ghassem Miremadi , Sharif University of Technology
Reza Farivar , Sharif University of Technology
pp. 266-274

Soft Errors induced by single heavy ions in Floating Gate memory arrays (Abstract)

A. Paccagnella , Padova University
M. Bonanomi , STMicroelectronics Central R&D
A. Visconti , STMicroelectronics Central R&D
G. Cellere , Padova University
pp. 275-284

On the Modeling and Analysis of Jitter in ATE Using Matlab (Abstract)

Fabrizio Lombardi , Northeastern University, Boston
Yong-Bin Kim , Northeastern University, Boston
Kyung Ki Kim , Northeastern University, Boston
Jing Huang , Northeastern University, Boston
pp. 285-293

Data Dependent Jitter (DDJ) Characterization Methodology (Abstract)

Yong-Bin Kim , Northeastern University, Boston
Fabrizio Lombardi , Northeastern University, Boston
Kyung Ki Kim , Northeastern University, Boston
pp. 294-304
Interactive Session

Reliable Digital Circuits Design using Sigma-Delta Modulated Signals (Abstract)

Luigi Carro , Universidade Federal do Rio Grande do Sul
Erik Schuler , Universidade Federal do Rio Grande do Sul
pp. 314-324

A Technique for Modular Design of Self-Checking Carry-Select Adder (Abstract)

P. K. Lala , University of Arkansas, Fayetteville
D. P. Vasudevan , University of Arkansas, Fayetteville
pp. 325-333

A model of soft error e.ects in generic IP processors (Abstract)

F. Salice , Politecnico di Milano
C. Bolchini , Politecnico di Milano
D. Sciuto , Politecnico di Milano
A. Miele , Politecnico di Milano
pp. 334-342

Implementation of Concurrent Checking Circuits by Independent Sub-circuits (Abstract)

Vladimir Ostrovsky , Bar-Ilan University, Ramat Gan
Ilya Levin , Bar-Ilan University, Ramat Gan
pp. 343-351

Multiple Transient Faults in Logic: An Issue for Next Generation ICs (Abstract)

Fabio Toma , DEIS, University of Bologna
Martin Oma? , DEIS, University of Bologna
Daniele Rossi , DEIS, University of Bologna
Cecilia Metra , DEIS, University of Bologna
pp. 352-360

Efficient Exact Spare Allocation via Boolean Satisfiability (Abstract)

Sy-Yen Kuo , National Taiwan University
Yao-Wen Huang , Institute of Information Science, Academia Sinica
Hung-Yau Lin , National Taiwan University
Fang Yu , Institute of Information Science, Academia Sinica
D. T. Lee , Institute of Information Science, Academia Sinica
Chung-Hung Tsai , Institute of Information Science, Academia Sinica
pp. 361-370

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits (Abstract)

J. Di , University of Arkansas
D. Vasudevan , University of Arkansas
P.K. Lala , University of Arkansas
pp. 371-379

Delay Test Generation with All Reachable Output Propagation and Multiple Excitations (Abstract)

Bhushan Vaidya , Northeastern University, Boston, MA
Mehdi B. Tahoori , Northeastern University, Boston, MA
pp. 380-388

Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment (Abstract)

Zainalabedin Navabi , Northeastern University
Fabrizio Lombardi , Northeastern University
Pedram A. Riahi , Northeastern University
pp. 389-397

On Generating Pseudo-Functional Delay Fault Tests for Scan Designs (Abstract)

Irith Pomeranz , Purdue University
Zhuo Zhang , University of Iowa
Sudhakar M. Reddy , University of Iowa
pp. 398-405

Should Illinois-Scan Based Architectures be Centralized or Distributed? (Abstract)

Narendra Devta-Prasanna , Univ. of Iowa, Iowa
Arun Gunda , LSI Logic Corp.
Ahmad Al-Yamani , KFUPM, Dhahran, Saudi Arabia
pp. 406-414

On Generating Tests to Cover Diverse Worst-Case Timing Corners (Abstract)

Sean Wu , ECE, UC-Santa Barbara
Li-C. Wang , ECE, UC-Santa Barbara
Charles H-P Wen , ECE, UC-Santa Barbara
Leonard Lee , ECE, UC-Santa Barbara
pp. 415-426
Approaches for Soft Error

Computing Cache Vulnerability to Transient Errors and Its Implication (Abstract)

Wei Zhang , ECE, Southern Illinois Univ. Carbondale
pp. 427-435

A design flow for protecting FPGA-based systems against single event upsets (Abstract)

L. Sterpone , Politecnico di Torino
M. Violante , Politecnico di Torino
pp. 436-444

An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors (Abstract)

M. Sonza Reorda , Politecnico di Torino
M. Violante , Politecnico di Torino
P. Bernardi , Politecnico di Torino
L. Bolzani , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
pp. 445-453

A Low Power Soft Error Suppression Technique for Dynamic Logic (Abstract)

Mehdi B. Tahoori , Northeastern University
Jeetendra Kumar , Analog Devices Inc.
pp. 454-462

Soft Error Modeling and Protection for Sequential Elements (Abstract)

Hossein Asadi , Northeastern University
Mehdi B. Tahoori , Northeastern University
pp. 463-474
On-line and Concurrent Fault Detection

Efficient Failure Detection in Pipelined Asynchronous Circuits (Abstract)

Song Peng , Cornell University
Rajit Manohar , Cornell University
pp. 484-493

On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors (Abstract)

M. Sonza Reorda , Politecnico di Torino
E. S?nchez , Politecnico di Torino
G. Squillero , Politecnico di Torino
pp. 494-504
Fault and Error Tolerant Systems

Analysis and Testing for Error Tolerant Motion Estimation (Abstract)

Hyukjune Chung , University of Southern California
Antonio Ortega , University of Southern California
pp. 514-522

Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms (Abstract)

In Suk Chong , University of Southern California
Antonio Ortega , University of Southern California
pp. 523-534
Test Scheduling and Software-based Test

Software-Based Self-Test for Pipelined Processors: A Case Study (Abstract)

M. Hatzimihail , University of Piraeus, Greece
M. Psarakis , University of Piraeus, Greece
A. Paschalis , University of Athens, Greece
D. Gizopoulos , University of Piraeus, Greece
G. Xenoulis , University of Piraeus, Greece
pp. 535-543

Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling (Abstract)

Krishnendu Chakrabarty , Duke University
Paul Rosinger , University of Southampton
Bashir M. Al-Hashimi , University of Southampton
Enkelejda Tafaj , University of Southampton
pp. 544-551

Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems (Abstract)

Chunsheng Liu , University of Nebraska-Lincoln
Vikram Iyengar , IBM Microelectronics
Kugesh Veeraraghavant , University of Nebraska-Lincoln
pp. 552-562
Testing and Design for Analog Circuits

Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress (Abstract)

Shaolei Quan , Michigan State University, USA
Meng-Yao Liu , Natinal Central University, Taiwan
Chin-Long Wey , Natinal Central University, Taiwan
pp. 563-572

A New Test Methodology For DNL Error In Flash ADC?s (Abstract)

Martin Margala , University of Rochester
John Liobe , University of Rochester
Quentin Diduck , University of Rochester
Michael Wieckowski , University of Rochester
pp. 582-590

A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test (Abstract)

Martin Margala , University of Rochester
Gregory J. Briggs , University of Rochester
Sadeka Ali , University of Rochester
pp. 591-600
Author Index

Author Index (Abstract)

pp. 601
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