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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2005)
Monterey, California
Oct. 3, 2005 to Oct. 5, 2005
ISBN: 0-7695-2464-8
pp: 169-177
TM Mak , DEIS Univ. of Bologna
J. M. Cazeaux , DEIS Univ. of Bologna
M. Oma? , DEIS Univ. of Bologna
C. Metra , DEIS Univ. of Bologna
D. Rossi , DEIS Univ. of Bologna
ABSTRACT
<p>We analyze the impact of clock faults on product quality and operation in the field. We show that clock faults could: i) give rise to min delay violations; ii) compromise the effectiveness of delay fault testing in screening out possible delay faults; iii) be missed by current functional testing (in addition to possibly be missed by structural testing, as proven in [15]). Therefore, new testing/DFT approaches are needed to avoid the dramatic impact of clock faults on product quality and operation in the field. Various possible approaches are discussed.</p>
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CITATION
TM Mak, J. M. Cazeaux, M. Oma?, C. Metra, D. Rossi, "The Other Side of the Timing Equation: a Result of Clock Faults", 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), vol. 00, no. , pp. 169-177, 2005, doi:10.1109/DFTVS.2005.65
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