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19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. (2004)
Cannes, France
Oct. 10, 2004 to Oct. 13, 2004
ISSN: 1550-5774
ISBN: 0-7695-2241-6
TABLE OF CONTENTS

Reliability and yield: a joint defect-oriented approach (PDF)

R. Barsky , Comput. Sci. Dept., Technion, Haifa, Israel
pp. 2-10

On the yield of compiler-based eSRAMs (PDF)

X. Wang , IBM Corp., Essex Junction, VT, USA
pp. 11-19

Failure factor based yield enhancement for SRAM designs (PDF)

Yu-Tsao Hsing , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chih-Wea Wang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Ching-Wei Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chih-Tsun Huang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Wen Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 20-28

Defect characterization for scaling of QCA devices [quantum dot cellular automata ] (PDF)

Jing Huang , Dept of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
M. Momenzadeh , Dept of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
M.B. Tahoori , Dept of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
F. Lombardi , Dept of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
pp. 30-38

A highly fault tolerant PLA architecture for failure-prone nanometer CMOS and novel quantum device technologies (PDF)

A. Schmid , Microelectron. Syst. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
Y. Leblebici , Microelectron. Syst. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
pp. 39-47

Probabilistic balancing of fault coverage and test cost in combined built-in self-test/automated test equipment testing environment (PDF)

Shanrui Zhang , Dept of Electr. & Comput. Eng., Missouri Univ., Rolla, MO, USA
Minsu Choi , Dept of Electr. & Comput. Eng., Missouri Univ., Rolla, MO, USA
pp. 48-56

Characteristics of fault-tolerant photodiode and photogate active pixel sensor (APS) (PDF)

M.L. La Haye , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
G.H. Chapman , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
C. Jung , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
D.Y.H. Cheung , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
S. Djaja , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
B. Wang , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
G. Liaw , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 58-66

Co-design and refinement for safety critical systems (PDF)

A. Ajer , Univ. of Sci. & Technol. of Lille 1, France
P. Devienne , Univ. of Sci. & Technol. of Lille 1, France
pp. 78-86

Noise effects on performance of low power design schemes in deep submicron regime [CMOS digital ICs] (PDF)

M. Abbas , Dept. of Electron. Eng., Univ. of Tokyo, Japan
M. Ikeda , Dept. of Electron. Eng., Univ. of Tokyo, Japan
K. Asada , Dept. of Electron. Eng., Univ. of Tokyo, Japan
pp. 87-95

On the defect tolerance of nano-scale two-dimensional crossbars (PDF)

Jing Huang , Dept of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
M.B. Tahoori , Dept of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
F. Lombardi , Dept of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
pp. 96-104

Monitoring methodology for TID damaging of SDRAM devices based on retention time analysis (PDF)

S. Bertazzoni , Dept. of Electron. Eng., Univ. di Roma, Italy
D. Di Giovenale , Dept. of Electron. Eng., Univ. di Roma, Italy
M. Salmeri , Dept. of Electron. Eng., Univ. di Roma, Italy
A. Mencattini , Dept. of Electron. Eng., Univ. di Roma, Italy
A. Salsano , Dept. of Electron. Eng., Univ. di Roma, Italy
M. Florean , Dept. of Electron. Eng., Univ. di Roma, Italy
pp. 106-110

Designs for reducing test time of distributed small embedded SRAMs (PDF)

B. Wang , Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
pp. 120-128

A fading algorithm for sequential fault diagnosis [logic IC testing] (PDF)

Shi-Yu Huang , Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Taiwan
pp. 139-147

Compression of VLSI test data by arithmetic coding (PDF)

H. Hashempour , Dept. of ECE, Northeastern Univ., Boston, MA, USA
F. Lombardi , Dept. of ECE, Northeastern Univ., Boston, MA, USA
pp. 150-157

Data integrity evaluations of Reed Solomon codes for storage systems [solid state mass memories] (PDF)

G.C. Cardarilli , Dept. of Electron. Eng., Rome Univ., Italy
M. Ottavi , Dept. of Electron. Eng., Rome Univ., Italy
S. Pontarelli , Dept. of Electron. Eng., Rome Univ., Italy
M. Re , Dept. of Electron. Eng., Rome Univ., Italy
A. Salsano , Dept. of Electron. Eng., Rome Univ., Italy
pp. 158-164

Modeling and analysis of crosstalk coupling effect on the victim interconnect using the ABCD network model (PDF)

A.K. Palit , ITEM, Bremen Univ., Germany
V. Meyer , ITEM, Bremen Univ., Germany
W. Anheier , ITEM, Bremen Univ., Germany
pp. 174-182

Reducing fault latency in concurrent on-line testing by using checking functions over internal lines (PDF)

I. Pomeranz , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 183-190

"Victim gate" crosstalk fault model (PDF)

M. Favalli , Ferrara Univ., Italy
pp. 191-199

Fast and low-cost clock deskew buffer (PDF)

M. Omana , DEIS, Bologna Univ., Italy
D. Rossi , DEIS, Bologna Univ., Italy
C. Metra , DEIS, Bologna Univ., Italy
pp. 202-210

Dynamic input match correction in RF low noise amplifiers (PDF)

T. Das , Dept. of Electr. Eng., Rochester Inst. of Technol., NY, USA
A. Gopalan , Dept. of Electr. Eng., Rochester Inst. of Technol., NY, USA
C. Washburn , Dept. of Electr. Eng., Rochester Inst. of Technol., NY, USA
P.R. Mukund , Dept. of Electr. Eng., Rochester Inst. of Technol., NY, USA
pp. 211-219

Mixed loopback BiST for RF digital transceivers (PDF)

J. Dabrowski , Dept. of Electr. Eng., Linkoping Univ., Sweden
J.G. Bayon , Dept. of Electr. Eng., Linkoping Univ., Sweden
pp. 220-228

Fault diagnosis of analog circuits by operation-region model and X-Y zoning method (PDF)

Y. Miura , Graduate Sch. of Eng., Tokyo Metropolitan Univ., Japan
pp. 230-238

Robust low-cost analog signal acquisition with self-test capabilities (PDF)

A.A. de Souza , Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
L. Carro , Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 239-247

A new approach to linear connections building BIST structure based on CSTP structure (PDF)

I. Gosciniak , Inst. of Comput. Sci., Univ. of Silesia, Katowice, Poland
pp. 256-263

Transient current testing of dynamic CMOS circuits (PDF)

N. Aaraj , Dept. of Electr. & Comput. Eng., American Univ. of Beirut, Lebanon
A. Nazer , Dept. of Electr. & Comput. Eng., American Univ. of Beirut, Lebanon
A. Chehab , Dept. of Electr. & Comput. Eng., American Univ. of Beirut, Lebanon
A. Kayssi , Dept. of Electr. & Comput. Eng., American Univ. of Beirut, Lebanon
pp. 264-271

IC HTOL test stress condition optimization (PDF)

B. Peng , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 272-279

Testing and defect tolerance: a Rent's rule based analysis and implications on nanoelectronics (PDF)

A. Kumar , Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA
S. Tiwari , Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA
pp. 280-288

Arithmetic operators robust to multiple simultaneous upsets (PDF)

C.A.L. Lisboa , Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
L. Carro , Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
pp. 289-297

Response compaction for test time and test pins reduction based on advanced convolutional codes (PDF)

Yinhe Han , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Yu Hu , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Huawei Li , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Xiaowei Li , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
pp. 298-305

An efficient perfect algorithm for memory repair problems (PDF)

Hung-Yau Lin , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 306-313

First level hold: a novel low-overhead delay fault testing technique (PDF)

S. Bhunia , Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
H. Mahmoodi , Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
A. Raychowdhury , Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy , Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 314-315

Error-resilient test data compression using Tunstall codes (PDF)

H. Hashempour , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
L. Schiano , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
F. Lombardi , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
pp. 316-323

Online testable reversible logic circuit design using NAND blocks (PDF)

D.P. Vasudevan , Dept. of Comput. Sci. & Comput. Eng., Arkansas Univ., Fayetteville, AR, USA
P.K. Lala , Dept. of Comput. Sci. & Comput. Eng., Arkansas Univ., Fayetteville, AR, USA
J.P. Parkerson , Dept. of Comput. Sci. & Comput. Eng., Arkansas Univ., Fayetteville, AR, USA
pp. 324-331

Toggle-masking for test-per-scan VLSI circuits (PDF)

N. Parimi , Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada
Xiaoling Sun , Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada
pp. 332-338

Learning based on fault injection and weight restriction for fault-tolerant Hopfield neural networks (PDF)

N. Kamiura , Dept. of Electr. Eng. & Comput. Sci., Univ. of Hyogo, Himeji, Japan
T. Isokawa , Dept. of Electr. Eng. & Comput. Sci., Univ. of Hyogo, Himeji, Japan
N. Matsui , Dept. of Electr. Eng. & Comput. Sci., Univ. of Hyogo, Himeji, Japan
pp. 339-346

Nonvolatile repair caches repair embedded SRAM and new nonvolatile memories (PDF)

J.Y. Fong , Texas Instrum. Inc., Dallas, TX, USA
R. Acklin , Texas Instrum. Inc., Dallas, TX, USA
J. Roscher , Texas Instrum. Inc., Dallas, TX, USA
pp. 347-355

Modeling yield of carbon-nanotube/silicon-nanowire FET-based nanoarray architecture with h-hot addressing scheme (PDF)

Shanrui Zhang , Dept. of Electr. & Comput. Eng., Missouri Univ., Rolla, MO, USA
Minsu Choi , Dept. of Electr. & Comput. Eng., Missouri Univ., Rolla, MO, USA
pp. 356-364

Annotated bit flip fault model (PDF)

M. Favalli , DI, Ferrara Univ., Italy
pp. 366-376

Accurate estimation of soft error rate (SER) in VLSI circuits (PDF)

A. Maheshwari , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
W. Burleson , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 377-385

At-speed functional verification of programmable devices (PDF)

N. Bombieri , Dipt. di Inf., Verona Univ., Italy
F. Fummi , Dipt. di Inf., Verona Univ., Italy
G. Pravadelli , Dipt. di Inf., Verona Univ., Italy
pp. 386-394

Incorporating signature-monitoring technique in VLIW processors (PDF)

Yung-Yuan Chen , Dept. of Comput. Sci. & Inf. Eng., Chung-Hua Univ., Hsin-Chu, Taiwan
Kun-Feng Chen , Dept. of Comput. Sci. & Inf. Eng., Chung-Hua Univ., Hsin-Chu, Taiwan
pp. 395-402

Exploiting an I-IP for in-field SoC test (PDF)

P. Bernardi , Politecnico di Torino, Italy
M. Rebaudengo , Politecnico di Torino, Italy
M.S. Reorda , Politecnico di Torino, Italy
pp. 404-412

Non-intrusive test compression for SOC using embedded FPGA core (PDF)

Gang Zeng , Graduate Sch. of Sci. & Technol., Chiba Univ., Japan
pp. 413-421

On-line analysis and perturbation of CAN networks (PDF)

M.S. Reorda , Politecnico di Torino, Italy
M. Violante , Politecnico di Torino, Italy
pp. 424-432

Reliable system co-design: the FIR case study (PDF)

C. Bolchini , Dipt. di Elettronica e Informazione, Politecnico di Milano, Italy
A. Miele , Dipt. di Elettronica e Informazione, Politecnico di Milano, Italy
F. Salice , Dipt. di Elettronica e Informazione, Politecnico di Milano, Italy
D. Sciuto , Dipt. di Elettronica e Informazione, Politecnico di Milano, Italy
pp. 433-441

Reliability modeling and assurance of clockless wave pipeline (PDF)

T. Feng , Dept. of Comput. Sci., Oklahoma State Univ., Stillwater, OK, USA
N. Park , Dept. of Comput. Sci., Oklahoma State Univ., Stillwater, OK, USA
pp. 442-450

System-level dependability analysis with RT-level fault injection accuracy (PDF)

R. Leveugle , TIMA Lab., Grenoble, France
D. Cimonnet , TIMA Lab., Grenoble, France
A. Ammari , TIMA Lab., Grenoble, France
pp. 451-458

A preliminary investigation of observation diversity for enhancing fortuitous detection of defects (PDF)

J. Dworak , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
J. Wingfield , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
M.R. Mercer , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 460-468

Concurrent on-line testing of identical circuits through output comparison using non-identical input vectors (PDF)

I. Pomeranz , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 469-476

An application-independent delay testing methodology for island-style FPGA (PDF)

Yen-Lin Peng , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Jing-Jia Liou , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chih-Tsun Huang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Wen Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 478-486

Reconfiguration algorithm for degradable processor arrays based on row and column rerouting (PDF)

M. Fukushi , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
S. Horiguchi , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
pp. 496-504
Session 13: System-on-Chip Test

Exploiting an I-IP for In-Field SOC Test (Abstract)

P. Bernardi , Politecnico di Torino, Italy
M. Rebaudengo , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
pp. 404-412

Non-Intrusive Test Compression for SOC Using Embedded FPGA Core (Abstract)

Gang Zeng , Chiba University, Japan
Hideo Ito , Chiba University, Japan
pp. 413-421
Session 14: Circuit and System Reliability and Dependability

On-Line Analysis and Perturbation of CAN Networks (Abstract)

M. Sonza Reorda , Politecnico di Torino, Italy
M. Violante , Politecnico di Torino, Italy
pp. 424-432

Reliable System Co-Design: The FIR Case Study (Abstract)

C. Bolchini , Politecnico di Milano
A. Miele , Politecnico di Milano
F. Salice , Politecnico di Milano
D. Sciuto , Politecnico di Milano
L. Pomante , CEFRIEL, Milano, Italy
pp. 433-441

Reliability Modeling and Assurance of Clockless Wave Pipeline (Abstract)

T. Feng , Oklahoma State University, Stillwater
N. Park , Oklahoma State University, Stillwater
Y. Kim , Northeastern University, Boston, MA
F. Lombardi , Northeastern University, Boston, MA
F. J. Meyer , Wichita State University, KS
pp. 442-450

System-Level Dependability Analysis with RT-Level Fault Injection Accuracy (Abstract)

R. Leveugle , TIMA Laboratory, France
D. Cimonnet , TIMA Laboratory, France
A. Ammari , TIMA Laboratory, France
pp. 451-458
Session 15: Novel Test Approaches

A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects (Abstract)

Jennifer Dworak , Texas A&M University, College Station, Texas
James Wingfield , Texas A&M University, College Station, Texas
M. Ray Mercer , Texas A&M University, College Station, Texas
pp. 460-468
Session 16: FPGA and Reconfigurable Circuits

An Application-Independent Delay Testing Methodology for Island-Style FPGA (Abstract)

Yen-Lin Peng , National Tsing Hua University, Hsinchu, Taiwan
Jing-Jia Liou , National Tsing Hua University, Hsinchu, Taiwan
Chih-Tsun Huang , National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Hsinchu, Taiwan
pp. 478-486

Author Index (PDF)

pp. 505-506
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