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19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. (2004)
Cannes, France
Oct. 10, 2004 to Oct. 13, 2004
ISSN: 1550-5774
ISBN: 0-7695-2241-6
TABLE OF CONTENTS

Reliability and yield: a joint defect-oriented approach (PDF)

R. Barsky , Comput. Sci. Dept., Technion, Haifa, Israel
pp. 2-10

On the yield of compiler-based eSRAMs (PDF)

X. Wang , IBM Corp., Essex Junction, VT, USA
pp. 11-19

Failure factor based yield enhancement for SRAM designs (PDF)

Yu-Tsao Hsing , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chih-Wea Wang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Ching-Wei Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chih-Tsun Huang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Wen Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 20-28

Defect characterization for scaling of QCA devices [quantum dot cellular automata ] (PDF)

Jing Huang , Dept of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
M. Momenzadeh , Dept of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
M.B. Tahoori , Dept of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
F. Lombardi , Dept of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
pp. 30-38

A highly fault tolerant PLA architecture for failure-prone nanometer CMOS and novel quantum device technologies (PDF)

A. Schmid , Microelectron. Syst. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
Y. Leblebici , Microelectron. Syst. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
pp. 39-47

Probabilistic balancing of fault coverage and test cost in combined built-in self-test/automated test equipment testing environment (PDF)

Shanrui Zhang , Dept of Electr. & Comput. Eng., Missouri Univ., Rolla, MO, USA
Minsu Choi , Dept of Electr. & Comput. Eng., Missouri Univ., Rolla, MO, USA
pp. 48-56

Characteristics of fault-tolerant photodiode and photogate active pixel sensor (APS) (PDF)

M.L. La Haye , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
G.H. Chapman , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
C. Jung , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
D.Y.H. Cheung , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
S. Djaja , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
B. Wang , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
G. Liaw , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 58-66

Co-design and refinement for safety critical systems (PDF)

A. Ajer , Univ. of Sci. & Technol. of Lille 1, France
P. Devienne , Univ. of Sci. & Technol. of Lille 1, France
pp. 78-86

Committees (PDF)

pp. xii
Session 1: Yield and Defects I

Reliability and Yield: A Joint Defect-Oriented Approach (Abstract)

Roman Barsky , Technion, Haifa, Israel
Israel A. Wagner , IBM Haifa Labs, Israel
pp. 2-10

On The Yield of Compiler-Based eSRAMs (Abstract)

X. Wang , IBM Corp, Essex Junction (VT) USA
M. Ottavi , Northeastern University Boston (MA) USA
F. Meyer , Wichita State University Wichita (KS) USA
F. Lombardi , Northeastern University Boston (MA) USA
pp. 11-19

Failure Factor Based Yield Enhancement for SRAM Designs (Abstract)

Yu-Tsao Hsing , National Tsing Hua University, Hsinchu, Taiwan
Chih-Wea Wang , National Tsing Hua University, Hsinchu, Taiwan
Ching-Wei Wu , National Tsing Hua University, Hsinchu, Taiwan
Chih-Tsun Huang , National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Hsinchu, Taiwan
pp. 20-28
Session 2: Yield and Defects II

Defect Characterization for Scaling of QCA Devices (Abstract)

Jing Huang , Northeastern University, Boston, MA
Mariam Momenzadeh , Northeastern University, Boston, MA
Mehdi B. Tahoori , Northeastern University, Boston, MA
Fabrizio Lombardi , Northeastern University, Boston, MA
pp. 30-38

A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies (Abstract)

Alexandre Schmid , Swiss Federal Institute of Technology EPFL, Switzerland
Yusuf Leblebici , Swiss Federal Institute of Technology EPFL, Switzerland
pp. 39-47

Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment (Abstract)

Shanrui Zhang , University of Missouri-Rolla
Minsu Choi , University of Missouri-Rolla
Nohpill Park , Oklahoma State University, Stillwater
Fabrizio Lombardi , Northeastern University, Boston
pp. 48-56
Session 3: Optoelectronics

Characteristics of Fault-Tolerant Photodiode and Photogate Active Pixel Sensor (APS) (Abstract)

Michelle L. La Haye , Simon Fraser University, Canada
Glenn H. Chapman , Simon Fraser University, Canada
Cory Jung , Simon Fraser University, Canada
Desmond Y. H. Cheung , Simon Fraser University, Canada
Sunjaya Djaja , Simon Fraser University, Canada
Benjamin Wang , Simon Fraser University, Canada
Gary Liaw , Simon Fraser University, Canada
Yves Audet , ?cole Polytechnique, Canada
pp. 58-66

Defect Avoidance in a 3-D Heterogeneous Sensor (Abstract)

Glenn H. Chapman , Simon Fraser University, Canada
Vijay Jain , University of South Florida, Tampa, Florida
pp. 67-75
Session 4: Defect and Fault Tolerance

Co-Design and Refinement for Safety Critical Systems (Abstract)

Ammar Aljer , University of Sciences and Technologies of Lille 1
Philippe Devienne , University of Sciences and Technologies of Lille 1
pp. 78-86

Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime (Abstract)

Mohamed Abbas , University of Tokyo, Japan
Makoto Ikeda , University of Tokyo, Japan
Kunihiro Asada , University of Tokyo, Japan
pp. 87-95

On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars (Abstract)

Jing Huang , Northeastern University, Boston, MA
Mehdi B. Tahoori , Northeastern University, Boston, MA
Fabrizio Lombardi , Northeastern University, Boston, MA
pp. 96-104
Session 5: Memory Test

Monitoring Methodology for TID Damaging of SDRAM Devices based on Retention Time Analysis (Abstract)

S. Bertazzoni , University of Rome "Tor Vergata", Italy
D. Di Giovenale , University of Rome "Tor Vergata", Italy
M. Salmeri , University of Rome "Tor Vergata", Italy
A. Mencattini , University of Rome "Tor Vergata", Italy
A. Salsano , University of Rome "Tor Vergata", Italy
M. Florean , University of Rome "Tor Vergata", Italy
J. Wyss , INFN Sezione di Pisa, Italy
R. Rando , INFN Sezione di Padova, Italy
S. Lora , Istituto per la Sintesi Organica e la Fotoreattivit?, Italy
pp. 106-110

Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs (Abstract)

X. Wang , IBM Corp, Essex Junction (VT) USA
M. Ottavi , Northeastern University Boston (MA) USA
F. Lombardi , Northeastern University Boston (MA) USA
pp. 111-119

Designs for Reducing Test Time of Distributed Small Embedded SRAMs (Abstract)

Baosheng Wang , University of British Columbia, Vancouver, Canada
Yuejian Wu , Nortel Networks, Ontario, Canada
Andr? Ivanov , University of British Columbia, Vancouver, Canada
pp. 120-128
Session 6: Diagnosis

An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost (Abstract)

Guido Bertoni , STMicroelectronics, Milano, Italy
Luca Breveglieri , Politecnico di Milano, Italy
Israel Koren , University of Massachusetts, Amherst
Paolo Maistri , Politecnico di Milano, Italy
pp. 130-138

A Fading Algorithm For Sequential Fault Diagnosis (Abstract)

Shi-Yu Huang , National Tsing-Hua University, Taiwan
pp. 139-147
Session 7: Error Correcting Codes

Compression of VLSI Test Data by Arithmetic Coding (Abstract)

H. Hashempour , Northeastern University, Boston, Mass
F. Lombardi , Northeastern University, Boston, Mass
pp. 150-157

Data Integrity Evaluations of Reed Solomon Codes for Storage Systems (Abstract)

G. C. Cardarilli , University of Rome "Tor Vergata", Italy
M. Ottavi , University of Rome "Tor Vergata", Italy
S. Pontarelli , University of Rome "Tor Vergata", Italy
M. Re , University of Rome "Tor Vergata", Italy
A. Salsano , University of Rome "Tor Vergata", Italy
pp. 158-164

An XOR Based Reed-Solomon Algorithm for Advanced RAID Systems (Abstract)

Ping-Hsun Hsieh , National Taiwan University, Taipei
Ing-Yi Chen , National Taipei University of Technology, Taiwan
Yu-Ting Lin , National Taiwan University, Taipei
Sy-Yen Kuo , National Taiwan University, Taipei
pp. 165-172
Session 8: Interconnect Faults

Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model (Abstract)

Ajoy K. Palit , University of Bremen, Germany
V. Meyer , University of Bremen, Germany
W. Anheier , University of Bremen, Germany
Juergen Schloeffel , Philips Semiconductors, Germany
pp. 174-182

Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines (Abstract)

Irith Pomeranz , Purdue University, W. Lafayette, IN
Sudhakar M. Reddy , University of Iowa, Iowa City
pp. 183-190

"Victim Gate" Crosstalk Fault Model (Abstract)

M. Favalli , DI - University of Ferrara, Italy
pp. 191-199
Session 9: RF and High Speed Circuits

Fast and Low-Cost Clock Deskew Buffer (Abstract)

Martin Oma? , D.E.I.S. University of Bologna, Italy
Daniele Rossi , D.E.I.S. University of Bologna, Italy
Cecilia Metra , D.E.I.S. University of Bologna, Italy
pp. 202-210

Dynamic Input Match Correction in RF Low Noise Amplifiers (Abstract)

Tejasvi Das , Rochester Institute of Technology
Anand Gopalan , Rochester Institute of Technology
Clyde Washburn , Rochester Institute of Technology
P. R. Mukund , Rochester Institute of Technology
pp. 211-219

Mixed Loopback BiST for RF Digital Transceivers (Abstract)

Jerzy Dabrowski , Link?ping University, Sweden
Javier Gonzalez Bayon , Link?ping University, Sweden
pp. 220-228
Session 10: Analog Testing

Robust Low-Cost Analog Signal Acquisition with Self-Test Capabilities (Abstract)

Ad?o A. de Souza Jr. , Instituto de Inform?tica -UFRGS. Porto Alegre, Brazil
Luigi Carro , Instituto de Inform?tica -UFRGS. Porto Alegre, Brazil
pp. 239-247
Session 11: Interactive Session

Coupling Different Methodologies to Validate Obsolete Microprocessors (Abstract)

L. Anghel , TIMA Laboratory, Grenoble, France
E. Sanchez , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
G. Squillero , Politecnico di Torino, Italy
R. Velazco , TIMA Laboratory, Grenoble, France
pp. 250-255

Transient Current Testing of Dynamic CMOS Circuits (Abstract)

Najwa Aaraj , American University of Beirut, Lebanon
Anis Nazer , American University of Beirut, Lebanon
Ali Chehab , American University of Beirut, Lebanon
Ayman Kayssi , American University of Beirut, Lebanon
pp. 264-271

IC HTOL Test Stress Condition Optimization (Abstract)

Brian Peng , National Taiwan University
Ing-Yi Chen , National Taipei University of Technology
Sy-Yen Kuo , National Taiwan University
Colin Bolger , VIA Technology Incorporation, Taiwan
pp. 272-279

Testing and Defect Tolerance: A Rent's Rule Based Analysis and Implications on Nanoelectronics (Abstract)

Arvind Kumar , Cornell University, Ithaca, NY
Sandip Tiwari , Cornell University, Ithaca, NY
pp. 280-288

Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes (Abstract)

Yinhe Han , Chinese Academy of Sciences, Beijing, China
Yu Hu , Chinese Academy of Sciences, Beijing, China
Huawei Li , Chinese Academy of Sciences, Beijing, China
Xiaowei Li , Chinese Academy of Sciences, Beijing, China
Anshuman Chandra , Synopsys, Inc., Mountain View, CA
pp. 298-305

An Efficient Perfect Algorithm for Memory Repair Problems (Abstract)

Hung-Yau Lin , National Taiwan University, Taipei
Fu-Min Yeh , Chung-Shan Institute of Science and Technology, Taoyuan, Taiwan
Ing-Yi Chen , University of Technology, Taipei, Taiwan
Sy-Yen Kuo , National Taiwan University, Taipei
pp. 306-313

First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique (PDF)

S. Bhunia , Purdue University, IN
H. Mahmoodi , Purdue University, IN
A. Raychowdhury , Purdue University, IN
K. Roy , Purdue University, IN
pp. 314-315

Error-Resilient Test Data Compression Using Tunstall Codes (Abstract)

H. Hashempour , Northeastern University, Boston, MA
L. Schiano , Northeastern University, Boston, MA
F. Lombardi , Northeastern University, Boston, MA
pp. 316-323

Online Testable Reversible Logic Circuit Design using NAND Blocks (Abstract)

D. P. Vasudevan , University of Arkansas, Fayetteville
P. K. Lala , University of Arkansas, Fayetteville
J. P. Parkerson , University of Arkansas, Fayetteville
pp. 324-331

Toggle-Masking for Test-per-Scan VLSI Circuits (Abstract)

Nitin Parimi , University of Alberta, Canada
Xiaoling Sun , University of Alberta, Canada
pp. 332-338

Learning Based on Fault Injection and Weight Restriction for Fault-Tolerant Hopfield Neural Networks (Abstract)

Naotake Kamiura , University of Hyogo, Japan
Teijiro Isokawa , University of Hyogo, Japan
Nobuyuki Matsui , University of Hyogo, Japan
pp. 339-346

Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories (Abstract)

John Y. Fong , Texas Instruments, Dallas, TX
Randy Acklin , Texas Instruments, Dallas, TX
John Roscher , Texas Instruments, Dallas, TX
Feng Li , Agilent Technologies, Santa Clara, CA
Cindy Laird , Agilent Technologies, Santa Clara, CA
Cezary Pietrzyk , Agilent Technologies, Santa Clara, CA
pp. 347-355

Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with h-hot Addressing Scheme (Abstract)

Shanrui Zhang , University of Missouri-Rolla
Minsu Choi , University of Missouri-Rolla
Nohpill Park , Oklahoma State University, Stillwater
pp. 356-364
Session 12: Error Detection and Correction

Annotated Bit Flip Fault Model (Abstract)

M. Favalli , DI - University of Ferrara, Italy
pp. 366-376

Accurate Estimation of Soft Error Rate (SER) in VLSI Circuits (Abstract)

Wayne Burleson , University of Massachusetts, Amherst
Israel Koren , University of Massachusetts, Amherst
Atul Maheshwari , University of Massachusetts, Amherst
pp. 377-385

At-Speed Functional Verification of Programmable Devices (Abstract)

Nicola Bombieri , Universit? di Verona
Franco Fummi , Universit? di Verona
Graziano Pravadelli , Universit? di Verona
pp. 386-394

Incorporating Signature-Monitoring Technique in VLIW Processors (Abstract)

Yung-Yuan Chen , Chung-Hua University, Hsin-Chu, Taiwan
Kun-Feng Chen , Chung-Hua University, Hsin-Chu, Taiwan
pp. 395-402
Session 13: System-on-Chip Test

Exploiting an I-IP for In-Field SOC Test (Abstract)

P. Bernardi , Politecnico di Torino, Italy
M. Rebaudengo , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
pp. 404-412

Non-Intrusive Test Compression for SOC Using Embedded FPGA Core (Abstract)

Gang Zeng , Chiba University, Japan
Hideo Ito , Chiba University, Japan
pp. 413-421
Session 14: Circuit and System Reliability and Dependability

On-Line Analysis and Perturbation of CAN Networks (Abstract)

M. Sonza Reorda , Politecnico di Torino, Italy
M. Violante , Politecnico di Torino, Italy
pp. 424-432

Reliable System Co-Design: The FIR Case Study (Abstract)

C. Bolchini , Politecnico di Milano
A. Miele , Politecnico di Milano
F. Salice , Politecnico di Milano
D. Sciuto , Politecnico di Milano
L. Pomante , CEFRIEL, Milano, Italy
pp. 433-441

Reliability Modeling and Assurance of Clockless Wave Pipeline (Abstract)

T. Feng , Oklahoma State University, Stillwater
N. Park , Oklahoma State University, Stillwater
Y. Kim , Northeastern University, Boston, MA
F. Lombardi , Northeastern University, Boston, MA
F. J. Meyer , Wichita State University, KS
pp. 442-450

System-Level Dependability Analysis with RT-Level Fault Injection Accuracy (Abstract)

R. Leveugle , TIMA Laboratory, France
D. Cimonnet , TIMA Laboratory, France
A. Ammari , TIMA Laboratory, France
pp. 451-458
Session 15: Novel Test Approaches

A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects (Abstract)

Jennifer Dworak , Texas A&M University, College Station, Texas
James Wingfield , Texas A&M University, College Station, Texas
M. Ray Mercer , Texas A&M University, College Station, Texas
pp. 460-468
Session 16: FPGA and Reconfigurable Circuits

An Application-Independent Delay Testing Methodology for Island-Style FPGA (Abstract)

Yen-Lin Peng , National Tsing Hua University, Hsinchu, Taiwan
Jing-Jia Liou , National Tsing Hua University, Hsinchu, Taiwan
Chih-Tsun Huang , National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Hsinchu, Taiwan
pp. 478-486

Author Index (PDF)

pp. 505-506
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