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Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems (2003)
Boston, Massachusetts
Nov. 3, 2003 to Nov. 5, 2003
ISSN: 1063-6722
ISBN: 0-7695-2042-1
TABLE OF CONTENTS
Introduction

Committees (PDF)

pp. xii
Session 1: Yield and Defects

Yield Analysis of Compiler-Based Arrays of Embedded SRAMs (Abstract)

X. Wang , Northeastern University
M. Ottavi , Northeastern University
F. Lombardi , Northeastern University
pp. 3

Reliability Estimation Model of ICs Interconnect Based on Uniform Distribution of Defects on a Chip (Abstract)

Tianxu Zhao , Baoji College of Arts and Sciences and Xidian University
Xuchao Duan , Baoji College of Arts and Sciences
Yue Hao , Xidian University
Peijun Ma , Xidian University
pp. 11

IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration (Abstract)

Meng Lu , Hyperchip Inc.
Yvon Savaria , Ecole Polytechnique de Montr?al
Bing Qiu , Hyperchip Inc.
Jacques Taillefer , Hyperchip Inc.
pp. 18

Calibration of Open Interconnect Yield Models (Abstract)

D. K. de Vries , Philips Semiconductors Crolles R&D
P. L. C. Simon , Philips Semiconductors Crolles R&D
pp. 26

Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults (Abstract)

T. Feng , Oklahoma State University
Y.B. Kim , Northeastern University
V. Piuri , University of Milan
pp. 34
Session 2: Optoelectronics

Level-Hybrid Optoelectronic TESH Interconnection Network (Abstract)

Vijay Jain , University of South Florida
Glenn Chapman , Simon Fraser University
pp. 45

Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS) (Abstract)

Sunjaya Djaja , Simon Fraser University
Glenn H. Chapman , Simon Fraser University
Desmond Y.H. Cheung , Simon Fraser University
Yves Audet , Ecole Polytechnique
pp. 53
Session 3: Fault Analysis, Injection & Simulation

Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors (Abstract)

C. Metra , University of Bologna
T.M. Mak , Intel Corporation
D. Rossi , University of Bologna
pp. 63

A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs (Abstract)

M. Alderighi , Istituto di Astrofisica Spaziale e Fisica Cosmica
F. Casini , Sanitas E.G. S.r.L.
S. D'Angelo , Istituto di Astrofisica Spaziale e Fisica Cosmica
M. Mancini , Istituto di Astrofisica Spaziale e Fisica Cosmica
A. Marmo , Universitá degli Studi di Milano
S. Pastore , Sanitas E.G. S.r.L.
G.R. Sechi , Istituto di Astrofisica Spaziale e Fisica Cosmica
pp. 71

CodSim — A Combined Delay Fault Simulator (Abstract)

Wangqi Qiu , Texas A&M University
Xiang Lu , Texas A&M University
Zhuo Li , Texas A&M University
D. M. H. Walker , Texas A&M University
Weiping Shi , Texas A&M University
pp. 79
Session 4: Test & Diagnosis

BIST Based Fault Diagnosis Using Ambiguous Test Set (Abstract)

Hiroshi Takahashi , Ehime University
Yasunori Tsugaoka , Ehime University
Hidekazu Ayano , Ehime University
Yuzo Takamatsu , Ehime University
pp. 89

On the Test and Diagnosis of the Perfect Shuffle (Abstract)

L. Schianoand , Northeastern University
F. Lombardi , Northeastern University
pp. 97

Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard (Abstract)

Guido Bertoni , Politecnico di Milano
Luca Breveglieri , Politecnico di Milano
Israel Koren , University of Massachusetts at Amherst
Paolo Maistri , Politecnico di Milano
Vincenzo Piuri , Università di Milano
pp. 105
Session 5: Current Test & Diagnosis

3DSDM: A 3 Data-Source Diagnostic Method (Abstract)

Y. Hariri , ?cole de Technologie Sup?rieure Montreal
C. Thibeault , ?cole de Technologie Sup?rieure Montreal
pp. 117

CROWNE: Current Ratio Outliers with Neighbor Estimator (Abstract)

Sagar S. Sabade , Texas A&M University
D. M. H. Walker , Texas A&M University
pp. 132
Session 6: Test Generation & Application

ATE-Amenable Test Data Compression with No Cyclic Scan (Abstract)

Hamidreza Hashempour , Northeastern University
Fabrizio Lombardi , Northeastern University
pp. 151

A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment (Abstract)

Fengming Zhang , Northeastern University
Y.J. Lee , Northeastern University
T. Kane , LTX Corporation
L. Schiano , Northeastern University
M. Momenzadeh , Northeastern University
Y-B Kim , Northeastern University
F.J. Meyer , Northeastern University
F. Lombardi , Northeastern University
S. Max , LTX Corporation
Phil Perkinson , LTX Corporation
pp. 159

Function-Based Dynamic Compaction and its Impact on Test Set Sizes (Abstract)

James Wingfield , Texas A&M University
Jennifer Dworak , Texas A&M University
M. Ray Mercer , Texas A&M University
pp. 167
Session 7: Scan Design & Test

Test Compaction by Using Linear-Matrix Driven Scan Chains (Abstract)

Sandeep Bhatia , Cadence Design Systems, Inc.
pp. 185
Session 8: BIST

Scan-Based BIST Diagnosis Using an Embedded Processor (Abstract)

Kedarnath J. Balakrishnan , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 209

Hybrid BIST Using an Incrementally Guided LFSR (Abstract)

C.V. Krishna , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 217

Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture (Abstract)

Gert Jervan , Link?ping University
Petru Eles , Link?ping University
Zebo Peng , Link?ping University
Raimund Ubar , Tallinn Technical University
Maksim Jenihhin , Tallinn Technical University
pp. 225
Session 9: Error Correcting Codes

Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols (Abstract)

Haruhiko Kaneko , Tokyo Institute of Technology
Eiji Fujiwara , Tokyo Institute of Technology
pp. 242

Quadruple Time Redundancy Adders (Abstract)

Whitney J. Townsend , University of Texas at Austin
Jacob A. Abraham , University of Texas at Austin
Earl E. Swartzlander, Jr. , University of Texas at Austin
pp. 250

Error Correcting Codes for Crosstalk Effect Minimization (Abstract)

D. Rossi , University of Bologna
S. Cavallotti , University of Bologna
C. Metra , University of Bologna
pp. 257
Invited Talk

A View from the Bottom: Nanometer Technology AC Parametric Failures — Why, Where, and How to Detect (Abstract)

Charles Hawkins , University of New Mexico
Ali Keshavarzi , Intel Corporation
Jaume Segura , University Balearic Islands
pp. 267
Session 10: Analogue & Mixed Signal Test

An Approach for Selection of Test Points for Analog Fault Diagnosis (Abstract)

Kranthi K. Pinjala , Arizona State University
Bruce C. Kim , Arizona State University
pp. 287

BiST Model for IC RF-Transceiver Front-End (Abstract)

Jerzy Dąbrowski , Link?ping University
pp. 295

A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits (Abstract)

John M. Emmert , Wright State University
Jason A. Cheatham , Wright State University
Badhri Jagannathan , Wright State University
Sandeep Umarani , Wright State University
pp. 303
Session 11: Defect Tolerance and Testing

Thermal Management of High Performance Microprocessors (Abstract)

Arman Vassighi , University of Waterloo
Oleg Semenov , University of Waterloo
Manoj Sachdev , University of Waterloo
Ali Keshavarzi , Intel Corporation
pp. 313

Fault Tolerant Multi-Layer Neural Networks with GA Training (Abstract)

Eiko Sugawara , Japan Aadvanced Institute of Science and Technology
Masaru Fukushi , Japan Aadvanced Institute of Science and Technology
Susumu Horiguchi , Japan Aadvanced Institute of Science and Technology
pp. 328

Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels (Abstract)

A. Ammari , TIMA Laboratory
R. Leveugle , TIMA Laboratory
M. Sonza-Reorda , Politecnico di Torino
M. Violante , Politecnico di Torino
pp. 336

Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture (Abstract)

Shervin Sharifi , University of Tehran
Mohammad Hosseinabadi , University of Tehran
Pedram Riahi , Northeastern University
Zainalabedin Navabi , University of Tehran
pp. 352

An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals (Abstract)

John M. Emmert , Wright State University
Jason A. Cheatham , Wright State University
Badhri Jagannathan , Wright State University
Sandeep Umarani , Wright State University
pp. 361

Fault Tolerant Hopfield Associative Memory on Torus (Abstract)

R. A. Ayoubi , University of Balamand
H. A. Ziade , Lebanese University
M. A. Bayoumi , University of Louisiana
pp. 369

Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study (Abstract)

B. Nicolescu , TIMA Laboratory
P. Peronnard , TIMA Laboratory
R. Velazco , TIMA Laboratory
Y. Savaria , Ecole Polytechnique de Montr?al
pp. 377

Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip (Abstract)

Anders Larsson , Link?pings Universitet
Erik Larsson , Link?pings Universitet
Petru Eles , Link?pings Universitet
Zebo Peng , Link?pings Universitet
pp. 385

Regressive Testing for System-on-Chip with Unknown-Good-Yield (Abstract)

N.-J. Park , Oklahoma State University
B. Jin , Oklahoma State University
K.M. George , Oklahoma State University
N. Park , Oklahoma State University
M. Choi , University of Missouri-Rolla
pp. 393

Error Detection in Signed Digit Arithmetic Circuit with Parity Checker (Abstract)

G.C. Cardarilli , University of Rome "Tor Vergata"
M. Ottavi , University of Rome "Tor Vergata"
S. Pontarelli , University of Rome "Tor Vergata"
M. Re , University of Rome "Tor Vergata"
A. Salsano , University of Rome "Tor Vergata"
pp. 401

Automatic Modification of Sequential Circuits for Self-Checking Implementation (Abstract)

Cecilia Metra , University of Bologna
Stefano Di Francescantonio , University of Bologna
Martin Omaña , University of Bologna
pp. 417

Control Constrained Resource Partitioning for Complex SoCs (Abstract)

Dan Zhao , State University of New York at Buffalo
Shambhu Upadhyaya , State University of New York at Buffalo
Martin Margala , University of Rochester
pp. 425

Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits (Abstract)

Kartik Mohanram , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 433
Session 12: FPGA & Memory Test

An Integrated Design Approach for Self-Checking FPGAs (Abstract)

C. Bolchini , Politecnico di Milano
F. Salice , Politecnico di Milano
D. Sciuto , Politecnico di Milano
R. Zavaglia , Politecnico di Milano
pp. 443

Power-Constrained Embedded Memory BIST Architecture (Abstract)

Bai Hong Fang , McMaster University
Nicola Nicolici , McMaster University
pp. 451

A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities (Abstract)

M. Nicolaidis , iRoC Technologies
N. Achouri , iRoC Technologies
L. Anghel , TIMA laboratory
pp. 459

Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator (Abstract)

Rob Aitken , Artisan Components
Neeraj Dogra , Artisan Components
Dhrumil Gandhi , Artisan Components
Scott Becker , Artisan Components
pp. 467

An Efficient Functional Test for the Massively-Parallel C ˙RAM Logic-Enhanced Memory Architecture (Abstract)

X. Sun , University of Alberta
B. F. Cockburn , University of Alberta
D. G. Elliott , University of Alberta
pp. 475
Session 13: Design Verification & Synthesis

Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models (Abstract)

Hamid R. Zarandi , Sharif University of Technology
Seyed Ghassem Miremadi , Sharif University of Technology
Alireza Ejlali , Sharif University of Technology
pp. 485

Preliminary Validation of an Approach Dealing with Processor Obsolescence (Abstract)

L. Anghel , TIMA Laboratory
R. Velazco , TIMA Laboratory
S. Saleh , TIMA Laboratory
S. Deswaertes , TIMA Laboratory
A. El Moucary , TIMA Laboratory
pp. 493
Session 14: SoC & Core Test

Embedded Compact Deterministic Test for IP-Protected Cores (Abstract)

Adam B. Kinsman , McMaster University
Jonathan I. Hewitt , McMaster University
Nicola Nicolici , McMaster University
pp. 519
Session 15: System Reliability

System-Level Analysis of Fault Effects in an Automotive Environment (Abstract)

F. Corno , Politecnico di Torino
S. Tosato , Politecnico di Torino
P. Gabrielli , Fiat Auto
pp. 529

Dependability Analysis of CAN Networks: An Emulation-Based Approach (Abstract)

J. P?rez , Universidad de la Rep?blica
M. Sonza Reorda , Politecnico di Torino
M. Violante , Politecnico di Torino
pp. 537
Session 16: Fault Tolerance

An Integrated Fault-Tolerant Design Framework for VLIW Processors (Abstract)

Yung-Yuan Chen , Chung-Hua University
Shi-Jinn Horng , National Taiwan University of Science & Technology
Hung-Chuan Lai , National Taiwan University of Science & Technology
pp. 555
Session 17: Soft Errors

Soft-Error Detection Using Control Flow Assertions (Abstract)

O. Goloubeva , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
M. Violante , Politecnico di Torino
pp. 581

SIED: Software Implemented Error Detection (Abstract)

B. Nicolescu , Ecole Polytechnique de Montr?al
Y. Savaria , Ecole Polytechnique de Montr?al
R. Velazco , TIMA Laboratory
pp. 589

Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits (Abstract)

Atul Maheshwari , University of Massachusetts at Amherst
Israel Koren , University of Massachusetts at Amherst
Wayne Burleson , University of Massachusetts at Amherst
pp. 597
Author Index

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