Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems (2003)
Nov. 3, 2003 to Nov. 5, 2003
James Wingfield , Texas A&M University
Jennifer Dworak , Texas A&M University
M. Ray Mercer , Texas A&M University
Due to the limited amount of available resources and time used for manufacture testing of integrated circuits, there is great interest in minimizing the number of test patterns applied while maintaining a large number of defect detections. Many methods have been developed to generate compact test pattern sets, and this paper extends the concepts of one such method (pattern-based dynamic compaction) into the functional realm. We will show that function-based dynamic compaction yields very compact test sets, and it retains compact performance for fault models of different difficulty.
M. R. Mercer, J. Dworak and J. Wingfield, "Function-Based Dynamic Compaction and its Impact on Test Set Sizes," Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems(DFT), Boston, Massachusetts, 2003, pp. 167.