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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2003)
Boston, Massachusetts
Nov. 3, 2003 to Nov. 5, 2003
ISSN: 1063-6722
ISBN: 0-7695-2042-1
pp: 167
M. Ray Mercer , Texas A&M University
Jennifer Dworak , Texas A&M University
James Wingfield , Texas A&M University
ABSTRACT
Due to the limited amount of available resources and time used for manufacture testing of integrated circuits, there is great interest in minimizing the number of test patterns applied while maintaining a large number of defect detections. Many methods have been developed to generate compact test pattern sets, and this paper extends the concepts of one such method (pattern-based dynamic compaction) into the functional realm. We will show that function-based dynamic compaction yields very compact test sets, and it retains compact performance for fault models of different difficulty.
INDEX TERMS
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CITATION
M. Ray Mercer, Jennifer Dworak, James Wingfield, "Function-Based Dynamic Compaction and its Impact on Test Set Sizes", 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), vol. 00, no. , pp. 167, 2003, doi:10.1109/DFTVS.2003.1250109
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