2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2003)
Nov. 3, 2003 to Nov. 5, 2003
C. Metra , University of Bologna
D. Rossi , University of Bologna
T.M. Mak , Intel Corporation
In this paper we analyze the fault effects of some clock calibration features which are common to today?s high performance microprocessors. We will show that induced faults with such schemes may give rise to effects that are not detectable by common manufacturing testing (e.g., scan based). However, these faults could seriously impact the microprocessor correct operation, and result in a decrease of product quality. Similar considerations may apply to different microprocessor calibration features. Considering that there is a wide range of process variations on die, as well as across the process, and that Very Deep Sub-Micron circuits tend to provide higher levels of performance to the circuits, the use of such on-die calibration features will increase in all segments of design. Proper strategies to test these features cannot be ignored.
C. Metra, D. Rossi, T.M. Mak, "Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors", 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), vol. 00, no. , pp. 63, 2003, doi:10.1109/DFTVS.2003.1250096