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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2002)
Vancouver, BC, Canada
Nov. 6, 2002 to Nov. 8, 2002
ISSN: 1063-6722
ISBN: 0-7695-1831-1
TABLE OF CONTENTS
Introduction

Program Committee (PDF)

pp. xiii

TTTC Information (PDF)

pp. 439
Session 1: Yield I

Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI (Abstract)

Manoj Sachdev , University of Waterloo
Ali Keshavarzi , Intel Corp
Arman Vassighi , University of Waterloo
Oleg Semenov , University of Waterloo
pp. 12

Yield Estimates for the TESH Multicomputer Network (Abstract)

B. M. Maziarz , University of South Florida
V. K. Jain , University of South Florida
pp. 20
Session 2: Crosstalk Faults

A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis (Abstract)

Massimo Violante , Politecnico di Torino
Luca Macchiarulo , Politecnico di Torino
Pierluigi Civera , Politecnico di Torino
pp. 31

A Test-Vector Generation Methodology for Crosstalk Noise Faults (Abstract)

Hamidreza Hashempour , Northeastern University
Yong-Bin Kim , Northeastern University
Naphill Park , Oklahoma State University
pp. 40
Session 3: Self-Checking and ABFT

A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard (Abstract)

Israel Koren , University of Massachusetts at Amherst
Vincenzo Piuri , University of Milan
Guido Bertoni , Politecnico di Milano
Paolo Maistri , Politecnico di Milano
Luca Breveglieri , Politecnico di Milano
pp. 51

Designing Self-Checking FPGAs through Error Detection Codes (Abstract)

Cristiana Bolchini , Politecnico di Milano
Donatella Sciuto , Politecnico di Milano
Fabio Salice , Politecnico di Milano
pp. 60

Self-Checking 1-out-of-n CMOS Current-Mode Checker (Abstract)

Jimson Mathew , Royal Institute of Technology
Elena Dubrova , Royal Institute of Technology
pp. 69

Partially Duplicated Code-Disjoint Carry-Skip Adder (Abstract)

E. S. Sogomonyan , University of Potsdam
V. Ocheretnij , University of Potsdam
D. Marienfeld , University of Potsdam
M. Gössel , University of Potsdam
pp. 78

Input Ordering in Concurrent Checkers to Reduce Power Consumption (Abstract)

Kartik Mohanram , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 87
Session 4: Fault Simulation and Injection I

Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied (Abstract)

A. Corominas , TIMA Laboratory
R. Velazco , TIMA Laboratory
P. Ferreyra , Universidad Nacional de C?rdoba
pp. 108

Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm (Abstract)

Jing-Reng Huang , National Tsing-Hua University
Horng-Bin Wang , National Tsing-Hua University
Shi-Yu Huang , National Tsing-Hua University
pp. 117
Session 5: Scan Design

Scan Architecture for Shift and Capture Cycle Power Reduction (Abstract)

Nicola Nicolici , McMaster University
Paul M. Rosinger , University of Southampton
Bashir M. Al-Hashimi , University of Southampton
pp. 129

Inserting Test Points to Control Peak Power During Scan Testing (Abstract)

Nur A. Touba , University of Texas at Austin
Ranganathan Sankaralingam , University of Texas at Austin
pp. 138
Session 6: Test Application

Matrix-Based Test Vector Decompression Using an Embedded Processor (Abstract)

Kedarnath J. Balakrishnan , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 159

Data Compression for System-on-Chip Testing Using ATE (Abstract)

W. Meleis , Northeastern University
Z. Navabi , Northeastern University
F. Karimi , LTX Corporation
F. Lombardi , Northeastern University
pp. 166
Session 7: Test Generation

Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults (Abstract)

Sooryong Lee , Texas A&M University
Li-C. Wang , University of California at Santa Barbara
M. Ray Mercerl , Texas A&M University
James Wingfield , Texas A&M University
Brad Cobb , Texas A&M University
Jennifer Dworak , Texas A&M University
pp. 177

Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE (Abstract)

H. Hashempour , Northeastern University
F. J. Meyer , Northeastern University
F. Lombardi , Northeastern University
pp. 186

Testing Digital Circuits with Constraints (Abstract)

Subhasish Mitra , Intel Corporation
Ahmad A. Al-Yamani , Stanford University
Edward J. McCluskey , Stanford University
pp. 195
Session 8: Concurrent Error Detection

A Memory Overhead valuation of the Interleaved Signature Instruction Stream (Abstract)

J. J. Serrano , Universidad Politécnica de Valencia
F. Rodríguez , Universidad Politécnica de Valencia
J. C. Campelo , Universidad Politécnica de Valencia
pp. 225

Fault-Tolerant CAM Architectures: A Design Framework (Abstract)

F. Salice , Politecnico di Milano
M. G. Sami , Politecnico di Milano
R. Stefanelli , Politecnico di Milano
pp. 233
Session 9: Fault Simulation and Injection II

Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes (Abstract)

Régis Leveugle , TIMA Laboratory
Béla Fehér , Budapest University of Technology and Economics
Lörinc Antoni , TIMA Laboratory and Budapest University of Technology and Economics
pp. 245

A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques (Abstract)

J. Gracia , Polytechnic University of Valencia
S. Blanc , Polytechnic University of Valencia
P. J. Gil , Polytechnic University of Valencia
pp. 254
Session 10: Interconnect

Performance of Deadlock-Free Adaptive Routing for Hieral.chical Interconnection Network TESH (Abstract)

Susumu Horiguchi , Japan Advanced Institute of Science and Technology
Yasuyuki Miura , Communication Research Laboratory
pp. 275

Testing Layered Interconnection Networks (Abstract)

N. Park , Oklahoma State University
F. Lombardi , Northeastern University
pp. 293
Session 11: Yield II

Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure (Abstract)

Kazunori Nemoto , Hitachi, Ltd.
Shiro Kamohara , Hitachi, Ltd.
Kousuke Okuyama , Hitachi, Ltd.
Hisafumi Iwata , Hitachi, Ltd.
Aritoshi Sugimoto , Hitachi, Ltd.
Takaaki Kumazawa , Hitachi, Ltd.
Yuichi Hamamura , Hitachi, Ltd.
pp. 305

Yield Modeling of a WSI Telecom Router Architecture (Abstract)

Claude Thibeault , Ecole de Technologie Superieure
Yvon Savaria , Ecole Polytechnique de Montreal
Chunyan Wang , Concordia University
Bing Qiu , Concordia University
Meng Lu , Ecole Polytechnique de Montreal
pp. 314
Session 12: System-on-Chip Test

Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation (Abstract)

Alex Orailoglu , University of California at San Diego
Ozgur Sinanoglu , University of California at San Diego
pp. 325

Adaptive Test Scheduling in SoC?s by Dynamic Partitioning (Abstract)

Shambhu Upadhyaya , State University of New York at Buffalo
Dan Zhao , State University of New York at Buffalo
pp. 334
Session 13: Feasibility of CED
Session 14: Test

Emulation-Based Design Errors Identification (Abstract)

F. Fummi , Universita di Verona
A. Castelnuovot , STMicroelectronics
F. Sforza , STMicroelectronics
A. Fin , Universita di Verona
pp. 365

A New Functional Fault Model for FPGA Application-Oriented Testing (Abstract)

M. Rebaudengo , Politecnico di Torino
M. Violante , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
pp. 372

CMOS Standard Cells Characterization for I<sub>DDQ</sub> Testing (Abstract)

Tomasz Borejko , Warsaw University of Technology
Wieslaw Kuzmicz , Warsaw University of Technology
Witold A. Pleskacz , Warsaw University of Technology
pp. 390

On-Chip Jitter Measurement for Phase Locked Loops (Abstract)

Jien-Chung Lo , University of Rhode Island
Tian Xia , University of Rhode Island
pp. 399

Neural Networks-Based Parametric Testing of Analog IC (Abstract)

V. Stopjaková , Slovak University of Technology
M. Margala , University of Rochester
L.' Beňuscaron;ková , Comenius University
D. Mičušík , Slovak University of Technology
pp. 408
Session 15: Reliable and Repairable Memories

Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems (Abstract)

V. Piuri , University of Milan
Y. B. Kim , Northeastern University
M. Choi , Oklahoma State University
N. Park , Oklahoma State University
F. Lombardi , Northeastern University
pp. 419

Repairability Evaluation of Embedded Multiple Region DRAMs (Abstract)

M. Choi , Oklahoma State University
Y. Chang , Oklahoma State University
F. Lombardi , Northeastern University
N. Park , Oklahoma State University
pp. 428
Author Index

Author Index (PDF)

pp. 437
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