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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2001)
San Francisco, California
Oct. 24, 2001 to Oct. 26, 2001
ISBN: 0-7695-1203-8
TABLE OF CONTENTS
Session 1: Wafer Scale

Advanced Fault-Tolerance Techniques for a Color Digital Camera-on-a-Chip (Abstract)

Zahava Koren , University of Massachusetts
Glenn Chapman , Simon Fraser University
Israel Koren , University of Massachusetts
pp. 0003

Challenges Facing Practical DFT for MEMS (Abstract)

S.K. Tewksbury , Stevens Institute of Technology
pp. 0011

Design of a Self-Correcting Active Pixel Sensor (Abstract)

Glenn H. Chapman , Simon Fraser University
Yves Audet , Ecole Polytechnique
pp. 0018
Session 2: Yield

Yield-Reliability Modeling for Fault Tolerant Integrated Circuits (Abstract)

Adit D. Singh , Auburn University
Victor P. Nelson , Auburn University
Thomas S. Barnett , Auburn University
pp. 0029

A Simple via Duplication Tool for Yield Enhancement (Abstract)

Neil Harrison , Philips Semiconductors
pp. 0039

Relation between Reliability and Yield of IC's Based on Discrete Defect Distribution Model (Abstract)

Taifeng Chen , Xidian University
Yue Hao , Xidian University
Tianxu Zhao , Xidian University
Peijun Ma , Xidian University
pp. 0048
Session 3: Dependable Design

On-Line Error Detectable Carry-Free Adder Design (Abstract)

A. Walker , North Carolina A&T State University
P.K. Lala , University of Arkansas
pp. 0066

Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic (Abstract)

Chen He , University of Texas at Austin
Tat Ngai , University of Texas at Austin
Earl E. Swartzlander Jr , University of Texas at Austin
pp. 0078
Session 4: Testing Techniques 1

Embedded Core Testing Using Broadcast Test Architecture (Abstract)

S. C. Chang , National Chung Cheng University
J. H. Jiang , National Chung Cheng University
W. B Jone , University of Cincinnati
pp. 0095

Analyzing BIST Robustness (Abstract)

Janusz Sosnowski , Warsaw University of Technology
pp. 0104

Test Pattern Decompression Using a Scan Chain (Abstract)

Jiri Nosek , Technical University Liberec
Ondrej Novak , Technical University Liberec
pp. 0110

Reducing Power Dissipation during At-Speed Test Application (Abstract)

Huawei Li , Chinese Academy of Sciences
Yinghua Min , Chinese Academy of Sciences
Xiaowei Li , Chinese Academy of Sciences
pp. 0116
Session 5: Fault-Tolerance in Arrays

Permanent Fault Repair for FPGAs with Limited Redundant Area (Abstract)

Edward J. McCluskey , Stanford University
Shu-Yi Yu , Stanford University
pp. 0125
Session 6: Fault Detection

Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays (Abstract)

W.K. Huang , Fudan Univ
X.T. Chen , Lucent Technologies
F.J. Meyer , Northeastern Univ
N. Park , Oklahoma State Univ
F. Lombardi , Northeastern Univ
pp. 0161

A Software Methodology for Detecting Hardware Faults in VLIW Data Paths (Abstract)

F. Salice , Politecnico di Milano
C. Bolchini , Politecnico di Milano
pp. 0170

Efficient Parity Prediction in FPGA (Abstract)

Seok-Bum Ko , University of Rhode Island
Jien-Chung Lo , University of Rhode Island
Xia Tian , University of Rhode Island
pp. 0176
Session 7: FPGA Based Applications

A Fault-Tolerance Strategy for an FPGA-Based Multi-stage Interconnection Network in a Multi-sensor System for Space Application (Abstract)

Fabio Casini , Istituto di Fisica Cosmica "G. Occhialini"
Giacomo R. Sechi , Istituto di Fisica Cosmica "G. Occhialini"
Sergio D'Angelo , Istituto di Fisica Cosmica "G. Occhialini"
Davide Salvi , Istituto di Fisica Cosmica "G. Occhialini"
Monica Alderighi , Istituto di Fisica Cosmica "G. Occhialini"
pp. 0191

Idle Cycles Based Concurrent Error Detection of RC6 Encryption (Abstract)

Kaijie Wu , Polytechnic University
Ramesh Karri , Polytechnic University
pp. 0200

Fast Run-Time Fault Location in Dependable FPGA-Based Applications (Abstract)

Wei-Je Huang , Stanford University
Subhasish Mitra , Stanford University
Edward J. McCluskey , Stanford University
pp. 0206

Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules (Abstract)

Pieter Trouborst , Nortel Networks
Jian Xu , University of Alberta
Xiaoling Sun , University of Alberta
pp. 0221
Session 8: Fault Injection

Comparison and Application of Different VHDL-Based Fault Injection Techniques (Abstract)

D. Gil , Universidad Polit?cnica de Valencia. Spain
J. Gracia , Universidad Polit?cnica de Valencia. Spain
J.C. Baraza , Universidad Polit?cnica de Valencia. Spain
P.J. Gil , Universidad Polit?cnica de Valencia. Spain
pp. 0233

Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits (Abstract)

P. Civera , Politecnico di Torino
M. Violante , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
L. Macchiarulo , Politecnico di Torino
pp. 0250

Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results (Abstract)

O. Calvo , Universidad de las Islas Baleares (U.I.B.)
R. Leveugle , TIMA Laboratory
R. Velazco , TIMA Laboratory
pp. 0259
Session 9: Testing Techniques 2

Parallel Testing of Multi-port Static Random Access Memories for BIST (Abstract)

F. Karimi , Northeastern University
F. Lombardi , Northeastern University
pp. 0271

A Speed-Dependent Approach for Delta IDDQ Implementation (Abstract)

Paul Lee , LSI Logic HongKong
Dilip Mathew , LSI Logic HongKong
Alfred Chen , LSI Logic HongKong
pp. 0280

Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field (Abstract)

Masaki Hashizume , Univ. of Tokushima
Taisuke Iwakiri , Univ. of Tokushima
Takeomi Tamesada , Univ. of Tokushima
Hiroyuki Yotsuyanagi , Univ. of Tokushima
Masahiro Ichimiya , Univ. of Tokushima
pp. 0287
Session 10: Error Correcting Codes

Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities (Abstract)

Eiji Fujiwara , Tokyo Institute of Technology
Kazuteru Namba , Tokyo Institute of Technology
pp. 0299

Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes (Abstract)

Abbas Dandache , University of Metz
Stanislaw J. Piestrak , Wroclaw University of Technology
Fabrice Monteiro , University of Metz
pp. 0314
Session 11: Mixed Signal Circuits

A Step Response Based Mixed-Signal BIST Approach (Abstract)

Alvernon Walker , North Carolina A&T State University
pp. 0329

Analog BIST Generator for ADC Testing (Abstract)

M. Renovell , University of Montpellier
F. Azaïs , University of Montpellier
Y. Bertrand , University of Montpellier
S. Bernard , University of Montpellier
pp. 0338

Reliability Enhancement of Analog-to-Digital Converters (ADCs) (Abstract)

Mandeep Singh , University of Massachusetts
Israel Koren , University of Massachusetts
pp. 0347
Session 12: Defect Analysis

Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects (Abstract)

T.M. Mak , Intel Corporation
B. Ricco' , University of Bologna
S. Di Francescantonio , University of Bologna
C. Metra , University of Bologna
pp. 0357

Defect Analysis and a New Fault Model for Multi-port SRAMs (Abstract)

Dean Adams , IBM Microelectronics
Pradeep Nagaraj , Qualcomm CDMA Technologies
Kamran Zarrineh , SUN Microelectronics
pp. 0366

CMOS Standard Cells Characterization for Defect Based Testing (Abstract)

Witold A. Pleskacz , Warsaw University of Technology
Wieslaw Kuzmicz , Warsaw University of Technology
Tomasz Oleszczak , Warsaw University of Technology
Dominik Kasprowicz , Warsaw University of Technology
pp. 0384
Session 13: Self-Checking and Fail-Safe Circuits

Survivable Self-Checking Sequential Circuits (Abstract)

S. Ostanin , Tel-Aviv University
A. Matrosova , Tomsk State University
I. Levin , Tel-Aviv University
pp. 0395

Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines (Abstract)

M. Ottavi , University of Rome
A. Salsano , University of Rome
G. C. Cardarilli , University of Rome
S. Pontarelli , University of Rome
D. Cellitti , University of Rome
M. Re , University of Rome
pp. 0403

How to Tune the MTTF of a Fail-Silent System (Abstract)

Andreas Steininger , Vienna University of Technology
Christoph Scherrer , Vienna University of Technology
pp. 0418
Session 14: Fault-Tolerant Techniques

Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture (Abstract)

Kaijie Wu , Polytechnic University
Ramesh Karri , Polytechnic University
Piyush Mishra , Polytechnic University
Yongkook Kim , IBM Corporation
pp. 0427

On Variable-Shift-Based Fault Compensation of Fuzzy Controllers (Abstract)

Masashi Tomita , Himeji Institute of Technology
Naotake Kamiura , Himeji Institute of Technology
Nobuyuki Matsui , Himeji Institute of Technology
Teijiro Isokawa , Himeji Institute of Technology
pp. 0436

On-Line Fault Tolerance for FPGA Interconnect with Roving STARs (Abstract)

John Emmert , UNC Charlotte
Andrew Taylor , UNC Charlotte
Charles Stroud , UNC Charlotte
Pankaj Kataria , UNC Charlotte
Stanley Baumgart , UNC Charlotte
Miron Abramovici , Agere Systems
pp. 0445

System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology (Abstract)

M. Ottavi , University of Rome
A. Malvoni , University of Rome
A. Salsano , University of Rome
M. Re , University of Rome
G.C. Cardarilli , University of Rome
S. Pontarelli , University of Rome
pp. 0455

Performance Evaluation of Checksum-Based ABFT (Abstract)

Ahmad A. Al-Yamani , Stanford University
Nahmsuk Oh , Stanford University
Edward J. McCluskey , Stanford University
pp. 0461

Author Index (PDF)

pp. 0467
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